Process for producing defect-free semiconductor devices having o

Details Process for producing defect-free semiconductor devices having o Process for producing defect-free semiconductor devices having o

1978-01-27

1979-04-17

Ozaki, G.

Metal treatment

Process of modifying or maintaining internal physical...

Chemical-heat removing or burning of metal

148189, 148 15, H01L 21223

Patent

active

041499158

ABSTRACT:
A process for fabricating devices having overlapping heavily doped impurity regions of opposite conductivity wherein the formation of crystallographic faults emanating from the overlapping regions is eliminated. It has been discovered that crystallographic faults can be avoided by limiting the total N and P impurity concentrations in the overlapped regions. The process includes forming in the semiconductor substrate a first arsenic doped region having a maximum impurity concentration in the range of 5.times.10.sup.20 to 3.times.10.sup.21 atoms/cc, and forming in the silicon substrate a second adjacent boron doped region in partial overlapping relation to the first region having a maximum impurity concentration in the range of 5.times.10.sup.19 to 3.times.10.sup.20 atoms/cc.

REFERENCES:
patent: 3491325 (1970-01-01), Hu
patent: 3770521 (1973-11-01), Demsky et al.
patent: 3798084 (1974-03-01), Lyons
patent: 3834953 (1974-09-01), Nakamura et al.
patent: 3879230 (1975-04-01), Nakamura et al.
patent: 3928091 (1975-12-01), Tachi et al.
patent: 3966514 (1976-06-01), Feng et al.
patent: 4049478 (1977-09-01), Ghosh et al.
Edel et al., "Stress Relief by Counterdoping", IBM Technical Disclosure Bulletin, vol. 13, No. 3, Aug. 1970, p. 632.
Edel, "Stacking Fault Free Epitaxial Layers", IBM Technical Disclosure Bulletin, vol. 14, No. 5, Oct. 1971, p. 1654.

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