Process for producing a uniform oxide layer on a compound semico

Details Process for producing a uniform oxide layer on a compound semico Process for producing a uniform oxide layer on a compound semico

1991-01-31

1993-05-25

Maples, John S.

Fishing, trapping, and vermin destroying

437946, 148DIG65, 148DIG118, 148DIG119, H01L 2102, H01L 2131

Patent

active

052140032

DESCRIPTION:

BRIEF SUMMARY
DESCRIPTION

1. TECHNICAL FIELD
This invention relates to a process for producing field-effect transistors (hereinafter referred to as FET) fabricated on substrates made from compound semiconductor single crystals and especially to a technique most effective for a case in which a MOSFET (Metal Oxide Semiconductor FET), Schottky diode or MESFET (Metal Semiconductor FET) is formed on a substrate made of InP single crystal, a ternary or quaternary mixed crystal with InP.
2. BACKGROUND ART
Since a compound semiconductor such as GaAs or InP has an electron mobility higher than that of silicon, as well as a superior radiation resistance and a superior heat resistance, such compound semiconductors are prospectively expected for high-frequency and high-speed electronic devices instead of silicon, and a lot of research has been performed. However, since a stable oxide film of a low interface trap density has not been obtained, a MOSFET with substrates of GaAs or InP single crystal has not yet been obtained. Thus, MESFETs with Schottky electrode, discrete high-frequency FETs and small-scale digital ICs (i.e., semiconductor integrated circuit) have in practice been devices with GaAs single crystal. However, a GaAs MESFET entails a drawback in that, since a Schottky barrier height therein is low, a logic amplitude cannot be high when an IC is made of the GaAs MESFET, and large-scale digital ICs cannot be produced at a high yield.
On the other hand, it has been held that only a MESFET having a Schottky barrier height lower than GaAs could be made as a device with a substrate made of InP single crystal. Thus, attempts have been made to produce a MOSFET in which a metal layer (i.e., electrode) is formed on an oxide layer deposited on an InP substrate by thermal oxidation, anodic oxidation or plasma oxidation method. However, all of these methods result in a nonuniform composition of the oxide layer, so that insulation performance of the layer is poor. Hence, a good MOSFET has not been achieved in practice. Instead of such methods of producing MOSFETs, many processes for producing a MISFET (Metal Insulator Semiconductor FET) have been studied, such as low temperature deposition of an insulating layer of SiO.sub.2, SiN.sub.x, Al.sub.2 O.sub.3 or PN on an InP substrate by CVD (Chemical Vapor Deposition), plasma CVD, light excitation CVD, sputtering, vapor deposition or spin-on method and forming of a metal layer on the insulating layer.
However, all of the MISFETs produced by the above methods are not used in practice, because they entail a fatal drawback in the electronic device in that a drain current drifts.
As described above, a MOSFET made from a compound semiconductor has not been practiced, because the composition of the oxide layer is nonuniform. It has been known, e.g., that thermally oxidizing InP in oxygen, first grows an about 20 .ANG. thick InPO.sub.4 layer and then deposits an In.sub.2 O.sub.3 layer outside the InPO.sub.4 layer and separates P (phosphorus) in an interface between InP and InPO.sub.4, because the diffusion rate of P is lower than that of In (Indium). Such a phenomenon takes place when any of the anodic oxidation and plasma oxidation methods are used, which results in a failure to obtain a uniform and good oxide layer.
Thus, since thermal oxidation makes it difficult to produce a good insulating layer, the various low temperature deposition methods described above have been studied. However, the deposition methods have a problem in that, since they deposit a material from a different family atop a compound semiconductor substrate, a lattice mismatching takes place in the interface between an insulating layer and the compound semiconductor substrate. Therefore, a surface defect, dirt etc . . . , readily produces many interface traps resulting in a drifting of the drain current.
On the other hand, an attempt of placing an approximately 30 .ANG. thick thin insulating layer (made, e.g., of Al.sub.2 O.sub.3, SiO.sub.2 or the like) between the InP substrate and the gate electrode metal has been made, i

REFERENCES:
patent: 4172906 (1979-10-01), Pancholy

Affiliated with

Also associated with

Rating

Process for producing a uniform oxide layer on a compound semico does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Process for producing a uniform oxide layer on a compound semico, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Process for producing a uniform oxide layer on a compound semico will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-897161