Process for producing a stacked capacitor having polysilicon wit

Details Process for producing a stacked capacitor having polysilicon wit Process for producing a stacked capacitor having polysilicon wit

1996-06-03

1997-04-08

Tsai, Jey

Semiconductor device manufacturing: process

Making passive device

Stacked capacitor

438255, 438684, H01L 2170, H01L 2700

Patent

active

056187475

ABSTRACT:
A process, and apparatus, for depositing hemispherical grained polysilicon layers, used for the fabrication of stacked capacitor structures, for DRAM devices, has been developed. The hemispherical grained polysilicon layer is deposited in an LPCVD tool, equipped with multiple heating zones, to allow the narrow temperature range needed for maximum surface roughness of the hemispherical grained polysilicon layers, to be obtained. In addition the LPCVD tool features multiple reactant injection inlets, reducing reactant concentration depletion across the length of the reaction zone, thus improving the uniformity of the hemispherical grained layers, from wafer to wafer.

REFERENCES:
patent: 5225378 (1993-07-01), Ushikawa
patent: 5278091 (1994-01-01), Fazan et al.
patent: 5290729 (1994-03-01), Hayashide et al.
patent: 5358883 (1994-10-01), Ahn et al.
patent: 5366919 (1994-11-01), Tanaka et al.
patent: 5369048 (1994-11-01), Hsue

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