Process for producing a multi-chip wiring arrangement

Details Process for producing a multi-chip wiring arrangement Process for producing a multi-chip wiring arrangement

1975-09-02

1977-07-12

Duzan, James R.

Metal working

Method of mechanical manufacture

Electrical device making

174 685, 427 96, 427 98, 361397, B41M 308

Patent

active

040344673

ABSTRACT:
A process for producing multi-chip wiring which facilitates high packing density and reliable flip-chip connections. In the process, an adhesive layer and a contact layer are vapor deposited onto a carrier. The desired structure of the connector path, outer contacts and connection surfaces are covered with a conductive layer and an intermediate layer with the aid of a first photo-lacquer mask by galvanic metal deposition. A solder-rejecting layer is galvanically deposited onto the structure of the conductor paths with the aid of a second photo-lacquer mask. The undesired regions of the adhesive layer and of the contact layer are etched away and the outer contacts and connection surfaces are covered with a solderable contact layer by selective currentless metal deposition.

REFERENCES:
patent: 3619725 (1971-11-01), Soden et al.
patent: 3672986 (1972-06-01), Schneble et al.
patent: 3773554 (1973-11-01), Scrutton et al.
patent: 3808049 (1974-04-01), Caley et al.
IBM J. Res. Develop., SLT Device and its Monolithic Extension, vol. 13, No. 3, May 1969, pp. 226-238.

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