Process for preparing complementary MOS integrated circuit

Details Process for preparing complementary MOS integrated circuit Process for preparing complementary MOS integrated circuit

1976-10-15

1978-04-18

Dost, Gerald A.

Metal working

Method of mechanical manufacture

Assembling or joining

357 42, B01J 1700

Patent

active

040843114

ABSTRACT:
A process for preparing a complementary MOS integrated circuit by forming a shallow first source-drain region near the gate; determining simultaneously the contact holes in the source-drain regions of both of the P-channel and N-channel transistors; forming a deep second source-drain region from the contact holes using thermal diffusion; and forming the electrodes at the contact holes.

REFERENCES:
patent: 3679492 (1972-07-01), Fang et al.
patent: 3775191 (1973-11-01), McQuhae

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