Process for preparing BiCMOS semiconductor device

Details Process for preparing BiCMOS semiconductor device Process for preparing BiCMOS semiconductor device

1991-11-01

1993-05-04

Hearn, Brian E.

Fishing, trapping, and vermin destroying

437 31, 437 45, 437 57, H01L 21265

Patent

active

052081710

ABSTRACT:
A process for preparing a BiCMOS semiconductor device having a MOS transistor element and a bipolar transistor element both of which are constituted in an epitaxial layer of n-type conductivity formed on a substrate of p-type conductivity, which comprises applying, after the formation of said epitaxial layer, an impurity ion of high energy simultaneously to specific of said epitaxial layer under which a channel region of said MOS transistor element and an emitter region of said bipolar transistor element are to be formed, thereby forming highly doped impurity regions around the bottom of said channel region and around the bottom of a base region of said bipolar transistor element.

REFERENCES:
patent: 4752589 (1988-06-01), Schaber
patent: 4806499 (1989-02-01), Shinohara
patent: 4879255 (1989-11-01), Deguchi et al.
patent: 4962052 (1990-10-01), Asayama et al.
patent: 4971921 (1990-11-01), Fukunaga et al.

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