Process for predicting propagation delay using linear interpolat

Details Process for predicting propagation delay using linear interpolat Process for predicting propagation delay using linear interpolat

1995-10-20

1997-05-20

Wieder, Kenneth A.

Electricity: measuring and testing

Impedance, admittance or other quantities representative of...

Parameter related to the reproduction or fidelity of a...

324532, 368120, 327 37, G04F 800

Patent

active

056315678

ABSTRACT:
According to the present invention, a process for use with automatic test equipment ("ATE") for determining a propagation delay in a semiconductor circuit is provided. In one embodiment of the invention, the process comprises the steps of determining an expected delay time by interpolating a first simulation capacitance, a second simulation capacitance, and an ATE capacitance, with a first simulated delay time and a second simulated delay time, the simulated delay times corresponding to the first and second simulated capacitances respectively, testing the semiconductor circuit with the ATE to determine an ATE delay time, and comparing the ATE delay time with the expected delay time to determine whether the propagation delay is acceptable.

REFERENCES:
patent: 4870629 (1989-09-01), Swerlein
patent: 5381100 (1995-01-01), Hayashi
patent: 5459402 (1995-10-01), Ueno
patent: 5488309 (1996-01-01), Farwell
patent: 5513152 (1996-04-01), Cabaniss

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