Process for positioning an electrical contact hole between two i

Details Process for positioning an electrical contact hole between two i Process for positioning an electrical contact hole between two i

1983-12-08

1985-05-21

Smith, John D.

Coating processes

Electrical product produced

Condenser or capacitor

156643, 156644, 156652, 156653, 427 90, 427 96, H01L 2188

Patent

active

045186294

ABSTRACT:
Process for positioning an electrical contact hole between a first and a second interconnection line of an integrated circuit. The first interconnection line is produced by depositing an insulating coating on the complete integrated circuit, depositing a first material coating on said insulating coating, etching the first material coating, defining the dimensions of the electrical contact hole by masking with resin, etching the insulating coating, eliminating the mask and the remaining first material coating.
The second interconnection line is produced by depositing a conductive coating on the complete integrated circuit, on which is deposited a second material coating, which is etched, so as to only leave material at the locations of the electrical contact hole, followed by the deposition of a resin coating, etching the area of the conductive coating where there is neither resin nor the residual second material coating and eliminating the latter and the resin coating.

REFERENCES:
patent: 4025411 (1977-05-01), Hom-Ma
patent: 4070501 (1978-01-01), Corbin et al.
patent: 4123565 (1978-10-01), Sumitomo
patent: 4185294 (1980-01-01), Sumitomo et al.
patent: 4305974 (1981-12-01), Abe
patent: 4321284 (1982-03-01), Yakushiji
patent: 4377438 (1983-03-01), Moriya
patent: 4430152 (1984-02-01), Okano
IBM Technical Disclosure Bulletin, vol. 24, No. 12, May 1982, pp. 6421-6422, R. K. Agnihotri et al.: "Planarization of Insulators for Submicro Multi-Level Structure".

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