Abrading – Abrading process – Glass or stone abrading
Reexamination Certificate
1999-06-24
2001-07-03
Young, Lee (Department: 3729)
Abrading
Abrading process
Glass or stone abrading
C451S005000, C451S006000, C451S008000
Reexamination Certificate
active
06254457
ABSTRACT:
CROSS-REFERENCE TO RELATED APPLICATIONS
This application is based upon and claims priority from prior French Patent Application No. 98-08152, filed Jun. 26, 1998, the entire disclosure of which is herein incorporated by reference.
FIELD OF THE INVENTION
The present invention relates to a process for polishing semiconductor wafers of integrated circuits during their fabrication.
BACKGROUND OF THE INVENTION
During the fabrication of integrated circuits on a silicon wafer, projecting features are produced, generally by etching. These are covered over the entire surface of the wafer with a coating of an external layer of a defined material. Next, a chemical-mechanical polishing operation is carried out so as to obtain a planar external surface on which the fabrication of the integrated circuits will continue.
Under particular polishing conditions, it is the polishing time which determines the position at the end of polishing of the polished external surface with respect to the subjacent projecting feature.
At the present time, this polishing time is determined, before carrying out the polishing of a batch of normally identical wafers, by experiments or by trial and error, by successively carrying out polishing operations and measurements of the remaining thickness of the covering material. This is what is proposed in particular in patent document EP 0,824,995.
Unfortunately, it turns out that a relatively high proportion of wafers have to be scrapped because the position of the polished external surface with respect to the subjacent projecting feature is outside preset limits.
Thus there is a need for a polishing process which would make it possible to improve the way the polished external surface is positioned with respect to the subjacent feature and consequently to reduce the proportion of wafers which do not satisfy the desired dimensional characteristics.
SUMMARY OF THE INVENTION
A process for polishing, on a polishing machine and under defined polishing conditions, the external surface of at least one wafer of integrated circuits comprising at least one projecting feature covered over the entire surface of the wafer with an external layer of a material and wherein the projecting feature has a main surface density (Dsp), the process comprising:
calculating a main equivalent thickness (Hea) by multiplying the main surface density (Dsp) of the projecting feature by the thickness (Hi) of the projecting feature;
polishing, under the defined polishing conditions, a reference wafer comprising an external layer of the material, having a uniform thickness and covering the surface of this reference wafer, so as to determine the rate of removal (V) by the polishing machine corresponding to the ratio of the thickness removed (Hr) to the polishing time elapsed (Tr);
calculating a polishing time (Tp) which is equal to the ratio of the equivalent thickness (Hea) to rate of removal (V); and
carrying out, under the polishing conditions, a polishing operation on at least one wafer to be polished for a duration that depends on the polishing time (Tp).
A process for polishing the external surface of at least one wafer of integrated circuits comprising a projecting feature covered over the entire surface of the wafer with an external layer of a material. The process, which is performed on a polishing machine and under defined polishing conditions, may comprise the following steps according to the invention: calculating a main equivalent thickness equal to the main surface density of the projecting feature multiplied by the thickness of the latter. The process can further include a step of polishing, under the defined polishing conditions, a reference wafer comprising an external layer of the material, which has a uniform thickness and covers the surface of this reference wafer, so as to determine the rate of removal by the polishing machine corresponding to the ratio of the thickness removed to the polishing time elapsed. A polishing time is calculated which is equal to the ratio of the aforementioned equivalent thickness to the aforementioned rate of removal; and in carrying out, under the polishing conditions, the polishing operation on at least one wafer to be polished for a duration which is equal to the aforementioned polishing time or which depends on this time.
Another possible process according to the invention may comprise: calculating a total equivalent thickness equal to the sum of the main equivalent thickness and of a complementary thickness of preset value; calculating a polishing time equal to the ratio of this total equivalent thickness to the aforementioned rate of removal; and carrying out, under the polishing conditions, the polishing operation on at least one wafer to be polished for a duration which is equal to this aforementioned polishing time or which depends on this time.
Another possible process according to the invention may comprise: measuring the remaining thickness, after polishing the covering material, on at least one polished wafer; subtracting this measured thickness from the desired thickness in order to obtain a correction thickness; calculating a total equivalent thickness equal to the sum of the correction thickness and of the equivalent thicknesses; calculating a polishing time equal to the ratio of this total equivalent thickness to the rate of removal; and carrying out, under the polishing conditions, the polishing operation on at least one wafer to be polished for a duration which is equal to this polishing time or which depends on this time.
According to one aspect of the invention, the complementary thickness is preferably obtained by measuring the thickness of the covering material between the projecting parts of the feature and by subtracting from this thickness the thickness of this feature and the desired thickness which has to remain above this feature.
According to another possible implementation of the invention, the complementary thickness is preferably obtained by measuring the thickness of the covering material above the projecting feature and by subtracting from this thickness the thickness of the projecting feature.
REFERENCES:
patent: 5240552 (1993-08-01), Yu et al.
patent: 5433650 (1995-07-01), Winebarger
patent: 5552996 (1996-09-01), Hoffman et al.
patent: 5618447 (1997-04-01), Sandhu
patent: 5655951 (1997-08-01), Meikle et al.
patent: 5659492 (1997-08-01), Li et al.
patent: 5664987 (1997-09-01), Renteln
patent: 5667629 (1997-09-01), Pan et al.
patent: 5685766 (1997-11-01), Mattingly et al.
patent: 5695601 (1997-12-01), Kodera et al.
patent: 5801066 (1998-09-01), Meikle
patent: 5812407 (1998-09-01), Sato et al.
patent: 5830041 (1998-11-01), Takahashi et al.
patent: 5851846 (1998-12-01), Matsui et al.
patent: 5938502 (1999-08-01), Kubo
patent: 5948203 (1999-09-01), Wang
patent: 5951370 (1999-09-01), Cesna
patent: 6004196 (1999-12-01), Doan et al.
patent: 6110008 (2000-08-01), Fujita et al.
patent: 6120348 (2000-09-01), Fujita et al.
patent: WO 97/01186 (1997-01-01), None
patent: WO 98/14306 (1998-04-01), None
French Search Report dated Mar. 8, 1999 with annex on French Application No. 98-08152.
Banvillet Henri
Liauzu Luc
Perrin Emmanuel
Robert Frédéric
Fleit Kain Gibbons Gutman & Bongini P.L.
Galanthay Theodore E.
STMicroelectronics S.A.
Trinh Minh
Young Lee
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