Semiconductor device manufacturing: process – Formation of electrically isolated lateral semiconductive... – Grooved and refilled with deposited dielectric material
Reexamination Certificate
2000-02-10
2001-06-12
Chaudhuri, Olik (Department: 2823)
Semiconductor device manufacturing: process
Formation of electrically isolated lateral semiconductive...
Grooved and refilled with deposited dielectric material
C438S437000, C438S693000, C438S703000
Reexamination Certificate
active
06245642
ABSTRACT:
CROSS-REFERENCE TO RELATED APPLICATION
This application is related to Japanese application No. HEI 11(1999)-078766 filed on Dec. 24, 1999, whose priority is claimed under 35 USC § 119, the disclosure of which is incorporated by reference in its entirety.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a process for manufacturing a semiconductor structure. More particularly, the process includes formation of a trench region for device isolation.
2. Description of Related Art
One of methods for forming a trench device isolation region has been disclosed in Japanese Unexamined Patent Publication No. HEI 9(1997)-153543. This conventional art is explained with reference to FIG.
2
.
First, a trench
32
is formed in a predetermined width and depth to a predetermined location on the surface of a silicon wafer
31
by use of a photolithography process (FIG.
2
(
a
)). Next, the resulting surface of the silicon wafer
31
is covered with a silicon oxide film
33
. This step is for filling the trench
32
with the silicon oxide film
33
and also covering the entire surface of the silicon wafer
31
with the silicon oxide film
33
of a predetermined thickness (FIG.
2
(
b
)).
The surface of the silicon oxide film
33
is flattened (FIG.
2
(
c
)) by chemical mechanical polishing using a slurry containing cerium oxide (CeO
2
). Further, the flattened silicon oxide film is polished with use of an abrasive slurry containing fumed silica so as to expose the surface of the silicon wafer
31
(FIG.
2
(
d
)). The ending of chemical mechanical polishing in this case can be judged from exposure of the surface of silicon wafer
31
, which is hydrophobic.
Next, the surface of the silicon wafer is subjected to finishing polish with use of an abrasive slurry of silicon compound containing an amine. As a result, a silicon wafer can be obtained which has a trench-isolated structure having a flat silicon surface and an isolation region of a silicon oxide film with rounded corners, but no dishing (FIG.
2
(
e
)).
Thus, in the case where the trench device isolation region embedded with the silicon oxide film is formed by the method of polishing with use of the cerium oxide-containing abrasive slurry and then polishing with use of the fumed silica-containing abrasive slurry, as disclosed by the above-mentioned Japanese Unexamined Patent Publication No. HEI 9(1997)-153543, fumed silica is used for polishing the silicon oxide film to expose the surface of silicon in an active region. However, since the fumed silica has a small selective ratio for a silicon wafer with respect to silicon oxide film, silicon of wafer cannot serve as a polish stopper. For this reason, the surface of silicon is over-polished, which results in a decrease in the depth of the trench.
SUMMARY OF THE INVENTION
The present invention provides a process for manufacturing a semiconductor structure comprising the steps of: (a) forming a first silicon nitride film on a semiconductor substrate; (b) patterning the first silicon nitride film into a predetermined configuration, etching the resulting semiconductor substrate using the first silicon nitride film as a mask to form a plurality of first trenches and at least one second trench, so as to form a first islands group and at least one second island-like region, the first islands group being composed of the plural first island-like regions located between the plural first trenches, and the second island-like region being adjacent to the first islands group with intervention of the second trench and being wider than the first island-like region; (c) depositing a silicon oxide film over the resulting surface to fill the first and second trenches with the silicon oxide film; (d) forming a second silicon nitride film over the resulting surface; (e) polishing the second silicon nitride film and the silicon oxide film by a CMP method using a first slurry until the surface of the first silicon nitride film on the second island-like region is exposed; (f) polishing the second silicon nitride film and the silicon oxide film by a CMP method using a second slurry until the surface of the first silicon nitride film on the first island-like region is exposed; (g) etching a predetermined amount of the silicon oxide film; and (h) removing the second silicon nitride film and the first silicon nitride film.
These and other objects of the present application will become more readily apparent from the detailed description given hereinafter. However, it should be understood that the detailed description and specific examples, while indicating preferred embodiments of the invention, are given by way of illustration only, since various changes and modifications within the spirit and scope of the invention will become apparent to those skilled in the art from this detailed description.
REFERENCES:
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patent: 5665202 (1997-09-01), Subramanian et al.
patent: 5721172 (1998-02-01), Jang et al.
patent: 5750433 (1998-05-01), Jo
patent: 5817567 (1998-10-01), Jang et al.
patent: 5958795 (1999-09-01), Chen et al.
patent: 6001740 (1999-12-01), Varian et al.
patent: 6048771 (2000-04-01), Lin et al.
patent: 6071792 (2000-06-01), Kim et al.
patent: 6146975 (2000-11-01), Kuchne et al.
patent: 9-153543 (1997-08-01), None
Chaudhuri Olik
Eaton Kurt
Nixon & Vanderhye P.C.
Sharp Kabushiki Kaisha
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