Process for planarization of integrated circuit structure...

Details Process for planarization of integrated circuit structure... Process for planarization of integrated circuit structure...

2000-09-13

2002-12-03

Kunemund, Robert (Department: 1765)

Semiconductor device manufacturing: process

Chemical etching

Combined with the removal of material by nonchemical means

C438S692000, C438S693000

Reexamination Certificate

active

06489242

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to planarization of dielectric material on an integrated circuit structure. More particularly this invention relates to an improved process for planarizing dielectric material which includes low k dielectric material which inhibits cracking of the low k dielectric material adjacent raised portions of the underlying integrated circuit structure.
2. Description of the Related Art
In the continuing reduction of scale in integrated circuit structures, both the width of metal interconnects or lines and the horizontal spacing between such metal lines on any particular level of such interconnects have become smaller and smaller. As a result, horizontal capacitance has increased between such conductive elements. This increase in capacitance, together with the vertical capacitance which exists between metal lines on different layers, results in loss of speed and increased cross-talk. As a result, reduction of such capacitance, particularly horizontal capacitance, has received much attention. One proposed approach to solving this problem of high capacitance is to replace the conventional silicon oxide (SiO
2
) dielectric material, having a dielectric constant (k) of about 4.0, with another dielectric material having a lower dielectric constant to thereby lower the capacitance.
In an article by L. Peters, entitled “Pursuing the Perfect Low-K Dielectric”, published in Semiconductor International, Volume 21, No. 10, September 1998, at pages 64—74, a number of alternate dielectric materials are disclosed and discussed. Included in these dielectric materials is a description of a low k dielectric material having a dielectric constant of about developed by Trikon Technologies of Newport, Gwent, U.K. The process is said to react methyl silane (CH
3—
SiH
3
) with hydrogen peroxide (H
2
O
2
) to form monosilicic acid which is annealed at 400° C. to remove moisture.
The incorporation of such carbon-doped silicon oxide dielectric material into interconnect architecture has been very attractive not only because of the low k properties, but also because of the compatibility with conventional silicon process technologies. Generally these materials remain stable upon annealing at temperatures of up to 500° C. The carbon doped silicon oxide materials are characterized by the structure of amorphous silicon oxide with incorporated methyl groups and hydrogen species, and are also characterized by a reduced density in comparison with conventional silicon oxide that can be explained by the formation of microporosity surrounding the incorporated methyl groups. Furthermore, such hydrocarbon-modified silicon oxide dielectric materials deposited by CVD techniques are also characterized by strong adhesion.
While such carbon-doped silicon oxide dielectric materials do exhibit the desired low k (i.e., dielectric constants below about 3.0) resulting in reduced capacitance of the dielectric material, it has been noted that cracking of the low k dielectric material sometimes occurs adjacent the regions of the layer of low k dielectric material formed over raised portions of the underlying integrated circuit structure. This cracking is particularly noted during or after planarization of the resulting structure using chemical mechanical polishing (CMP) processing.
One of the reasons for this cracking of the low k dielectric material during or after CMP planarization appears to be related to the tendency of the low k dielectric material to accumulate or “pile-up” over the raised underlying portions of the integrated circuit structure (such as a grouping of metal pads, or even more severely over wide lines) resulting in the need to remove an excessive amount of such low k dielectric material during the CMP planarization step, which, in turn, is believed to cause stresses in the low k dielectric layer being polished due to the nature of the CMP process.
Prior art
FIGS. 1 and 2
illustrate the problem.
FIG. 1
shows a typical integrated circuit structure at
2
having raised wide portions
4
such as metal pads or other wide structure formed thereon. Formed over raised portions
4
and underlying structure
2
is a composite layer of dielectric material comprising a thin base layer
6
of dielectric material, a low k carbon-doped silicon oxide dielectric layer
10
, and a thin capping layer
16
of dielectric material. Base layer
6
and capping layer
16
, which may comprise conventional silicon oxide, serve to protect the surfaces of low k dielectric layer
10
, as well as to facilitate adherence of the layer of low k material to other layers of the integrated circuit structure. A planarization layer
20
comprising, for example, any conventionally formed silicon oxide, is deposited over capping layer
16
and the structure is then planarized by subjecting it to a CMP process.
In order to planarize the structure down to the level of planarization layer
20
shown at arrow A (where there are no raised features in the underlying integrated circuit structure), it is necessary to remove a considerable amount of the portion of planarization layer
20
lying over raised portions
4
. In fact, as shown in
FIG. 2
, it is even necessary to removed some of underlying capping layer
16
and low k layer
10
to complete the planarization. The planarization process thus must be carried on for an extended period of time, which, in turn, results in an extended period of time during which the structure is under mechanical stress in order to remove the excessive amount of dielectric material over raised portions
4
. This, it is believed, results in the formation of cracks in the low k dielectric material which appear most often adjacent extending from the edges of the raised portions, as shown by the dotted lines labelled B in FIG.
2
. It would, therefore, be desirable to provide a planarization process wherein the upper surface of one or more dielectric layers formed over an integrated circuit structure having raised portions would be planarized, for example, to facilitate further photolithography, without however resulting in such undesirable cracking of the dielectric materials such as low k dielectric layer
10
.
SUMMARY OF THE INVENTION
In accordance with the invention, an planarization process is provided for an integrated circuit structure which inhibits or prevents cracking of low k dielectric material which comprises one of one or more layers of dielectric material formed over raised portions of the underlying integrated circuit structure. Prior to the planarization step, a removable mask is formed over one or more of the dielectric layers formed over raised portions of the integrated circuit structure. Openings are formed in the mask to expose the upper surface of the one or more dielectric layers in the region over at least some of these raised portions of the integrated circuit structure. Exposed portions of the underlying one or more dielectric layers are then etched through such openings in the mask to reduce the overall amount or volume of the one or more dielectric layers overlying such raised portions of the integrated circuit structure. The mask is then removed and the structure is subject to a chemical mechanical polishing step to planarize the upper surface of the structure. The prior removal, before the planarization step, of a portion of the overall amount or volume of the one or more dielectric layers in the region overlying the raised portions of the integrated circuit redistributes the stresses and structure results in a shortening of the CMP process which, in turn, results in a shortening of the time during which the structure is subject to the mechanical stresses of the CMP process. This inhibits or eliminates cracking of the low k dielectric layer adjacent the region of the low k dielectric layer over raised portions of the underlying integrated circuit structure.


REFERENCES:
patent: 3652331 (1972-03-01), Yamazaki
patent: 5314845 (1994-05-01), Lee et al.
patent: 5376595 (1994-12-01), Zupancic et al.
patent: 5558718 (1996-09-01

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