Boots – shoes – and leggings
Patent
1994-10-18
1997-05-13
Coleman, Eric
Boots, shoes, and leggings
364DIG1, G06F 1580
Patent
active
056301561
ABSTRACT:
Improved process for parallel operation of several computation units, especially in image processing, and corresponding architecture. Several computation units which are together intended to evaluate in an iterative and cellular manner the convergence values of a plurality of variables associated respectively with the various points of a predetermined grid each variable having to satisfy a prespecified iterative relation between itself and n neighbouring variables associated with n neighbouring grid points (P2-P5), a memory means is assigned per point of the grid, intended to store successively all the values of the variable associated with this grid point, the computation units are apportioned in such a way as to assign every grid point to a computation unit and two distinct computation units to two chosen neighbouring points of the grid, all the computation units are made to operate in parallel and independently of one another, and for each current point of the grid, the computation unit assigned to this current point is made to compute each successive value of the variable associated with this current point on the basis of the value contained in the memory means assigned to the current point and of those available and arising from the memory means assigned to the points neighbouring the current point, irrespective of the iteration levels to which these available values correspond, and the said computation unit is made to store each new value thus computed in the memory means associated with the current point.
REFERENCES:
patent: 4591980 (1986-05-01), Huberman
patent: 4835680 (1989-05-01), Hogg
patent: 5040214 (1991-08-01), Grossberg
patent: 5065308 (1991-11-01), Evans
patent: 5093781 (1992-03-01), Castelaz
patent: 5140670 (1992-08-01), Chua
patent: 5243551 (1993-09-01), Knowles
patent: 5253363 (1993-10-01), Hyman
patent: 5305395 (1994-04-01), Mahoney
1989 IEE International Symposium on Circuits and Systems vol. 1, pp. 13-16.
Proceedings of the 1986 International Conference on Parallel Processing pp. 343-350.
Proceedings of the 1986 International Conference on Systems, Man, and Cybernetics pp. 313-318.
Parallel Algorithms & Architectures pp. 169-188.
Microprocessors and Microsystems pp. 403-415 vol. 16, No. 8.
Planet Patricia
Privat Gilles
Renaudin Marc
Coleman Eric
France Telecom
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