Process for packaging a semiconductor die using dicing and testi

Details Process for packaging a semiconductor die using dicing and testi Process for packaging a semiconductor die using dicing and testi

1995-12-18

1998-12-22

Graybill, David

Semiconductor device manufacturing: process

With measuring or testing

Packaging or treatment of packaged semiconductor

438107, 438108, 438109, 438113, 438114, 438977, H01L 2158, H01L 2160, H01L 2170

Patent

active

058518452

ABSTRACT:
A method for packaging semiconductor dice is provided. The package includes a thinned die mounted on a compliant adhesive layer to a substrate. The package is formed by providing a wafer containing a plurality of dice, thinning a backside of the wafer by etching or polishing, attaching the thinned wafer to the substrate, and then dicing the wafer. The semiconductor package can be mounted to a supporting substrate such as a printed circuit board in a chip-on-board configuration. The compliant adhesive layer and substrate of the package eliminate stresses and cracking of the die caused by a thermal mismatch between the die and supporting substrate. In addition, the semiconductor package can be mounted in a flip chip configuration with the substrate for the package protecting a backside of the die from radiation.

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