Multiplex communications – Pathfinding or routing – Switching a message which includes an address header
Reexamination Certificate
1998-10-01
2003-04-22
Olms, Douglas (Department: 2661)
Multiplex communications
Pathfinding or routing
Switching a message which includes an address header
C370S535000
Reexamination Certificate
active
06553033
ABSTRACT:
BACKGROUND OF THE INVENTION
The invention relates to a process for transmitting ATM cells.
In contemporary ATM systems, information is transmitted in cells. These cells have a header part and an information part. In the header part, the connection information is deposited and in the information part, the user data to be transmitted are deposited. As a rule, the actual transmission takes place via connection elements between transmitter and receiver. In this arrangement, the requirement may exist that the connection elements should be utilized in such a manner that a multiplicity of transmitting devices transmit the cell streams emanating from them via the same connection element.
In order to be able to perform the transmission of the respective cell streams in accordance with the requirements of the individual cell streams, so-called scheduling processes have gained acceptance in the prior art. In these processes, the ATM cells are read out of the buffer memories of a scheduler device in a particular order. The WEIGHTED FAIR QUEUEING SCHEDULING process shall be mentioned as an example of such a scheduling process. The corresponding relationships are mentioned, for example, in the printed document “Spacing for Flexible Traffic Control”, J. W. Roberts, International Journal of Communication Systems, Vol. 7, 307 -318 (1994). In this document, individual cell streams are allocated different weighting factors by means of which the actual transmission process is controlled in the individual connection elements. To gain a better understanding, reference is made to FIG.
3
.
In this figure, cell streams
1
. . . n are disclosed by way of example. The n cell streams are conducted in the direction of one or more receivers by a transmitting device DEMUX. In practice, only one common connection element is used in this arrangement. The n cell streams are also allocated weighting factors r
1
. . . r
n
. To make it simpler to understand, it will be assumed that only two cell streams are to be conducted via one connection element, namely cell streams
1
,
2
. In addition, the connection element shall have a maximum transmission capacity of 150 Mbit/sec. Both cell streams
1
and
2
are allocated weightings r
1
=2 and r
2
=1. The result is that cell stream
1
is transmitted with a transmission rate of 100 Mbit/sec and cell stream
2
is transmitted with only 50 Mbit/sec if cells are present to be transmitted.
The problem with such a procedure is that many of the scheduling processes, such as, for example, the WEIGHTED FAIR QUEUEING SCHEDULING process explained above, cannot ensure peak bit rate limiting on the subsequent connection elements. To prevent any overloading, ATM cells are then discarded. Although this can be tolerated quite easily in the individual case (e.g. telephony), such a procedure should be avoided since it is always associated with a loss of data.
The invention is based on the object of demonstrating an approach of how the cell rates can be optimally matched to the transmission capacity of the connection elements without having to accept the loss of ATM cells.
The invention is achieved by the features of the characterizing clause on the basis of the features specified in the precharacterizing clause of claim
1
.
Furthermore, a method for the statistical multiplexing of ATM cells is specified in the printed document “Performance Design of an ATM Node on the Basis of the Experience from the BLNT RACE Project”, H. Heiss, E. Wallmeier et al., European Transactions on Telecommunications and Related Technologies, Vol. 5, No. 2, 1,3,49, pages 199-206. In particular, the known leaky bucket process is addressed which utilizes up/down counters. This method cannot be used for efficient processing of the ATM cells since, as a result of this method, ATM cells must always be discarded here.
Furthermore, European Patent Application EP 0 710 046 A2 discloses a device in which ATM cells are supplied to subsequent devices. However, this printed document does not reveal how this is to be performed in detail.
SUMMARY OF THE INVENTION
The invention is based on the object of demonstrating an approach of how the cell rates can be optimally matched to the transmission capacity of the connection elements without having to accept the loss of ATM cells.
In general terms the present invention is a process for the transmission of ATM cells via connection elements. Multiplexing units and/or demultiplexing units and scheduler devices are arranged between these units and have buffer memories. A stream of ATM cells is allocated a multiplicity of virtual channel identifiers and virtual paths combining these virtual channel identifiers. Arbitrarily adjustable weighting factors representative of the transmission capacity on the subsequent connection elements are allocated to the scheduler devices. One of the scheduler devices is selected as determined by the allocated weighting factors. At least one of the ATM cells is taken from one of the buffer memories of the selected scheduler device and is supplied to other devices.
Advantageous developments of the present invention are as follows.
The ATM cells stored in the buffer memories of the scheduler devices are taken by the WEIGHTED FAIR QUEUEING SCHEDULING process.
Real-time ATM cells are supplied via a separate connection element arranged in parallel with the scheduler devices to the multiplexer with higher prioritization than is exhibited by the ATM cells transmitted via the scheduler devices.
The buffer memories are constructed as FIFO memories.
The advantageous feature of the invention is, in particular, the use of a two-stage process which is executed sequentially. In this arrangement, the scheduler devices which have accepted ATM cells as queues in their buffer memories are selected in the first process step of the two-stage process. In the second process step, one of these buffer memories is then selected and at least one of the ATM cells is read out and transmitted. The advantageous feature of this is, in particular, that the first process step limits the peak bit rate of an ATM cell stream having one or more virtual channel identifiers. Furthermore, this process step is independent of the scheduling processes used in the second process step.
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9thITC Specialists Seminar Teletraffic Modeling and Measurement Broadband and Mobile Communications, Eugen Wallmeier et al, “Traffic Control In ATM Switches With Large Buffers”, pp. 45-60.
European Transactions on Telecommunications and Related Technologies, vol. 5, No. 2, Mar./Apr. (1994), Herbert Heiss et al, “Performance Design of an ATM Node on the Basis of the Experience from the BLNT RACE Project”, pp. 199-206.
IEEE, Discovering A New World of Communications, Chicago, vol. 2, No. 4, Jun. (1992), Michael G. Hluchyj et al, Queueing Disciplines for Integrated Fast Packet Networks, pp. 990-996.
International Journal of Communication systems, vol. 7, (1994), J. W. Roberts, “Virtual Spacing for Flexible Traffic Control”, pp. 307-318.
Fish & Richardson P.C.
Olms Douglas
Sam Phirin
Siemens Aktiengesellschaft
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