Process for operating a semiconductor device

Details Process for operating a semiconductor device Process for operating a semiconductor device

2000-04-03

2001-10-23

Fears, Terrell W. (Department: 2824)

Static information storage and retrieval

Floating gate

Particular biasing

C365S189090

Reexamination Certificate

active

06307782

ABSTRACT:

FIELD OF THE INVENTION
The invention relates in general to semiconductor devices and more particularly to processes for operating programmable cells within semiconductor devices.
RELATED ART
Floating gate memory cells are used as nonvolatile memory cells in many applications. Due to scaling requirements, including thinning of tunnel dielectric layers, the use of conventional floating gate memories may prove to be impossible from a practical standpoint. Because of point defects within the tunnel dielectric layer, unintended electrical shorts or leakage paths between the floating gate and substrate may form and cause undesirable electrical characteristics of the memory cell. Operating the floating gate memory cells typically is performed by programming, erasing, and reading the memory cells. Programming is typically performed by hot carrier injection or Fowler-Nordheim tunneling. In the case of hot electron injection, typically, the source is grounded, the drain region placed at potential of approximately 5-7 volts, and the control gate for the memory cell is placed at a potential of approximately 6-8 volts for a time of approximately 10 microseconds. Usually, the drain current during hot electron injection is greater than approximately 500 microamperes. Obviously, this depends on the geometries of the memory cell. For Fowler-Nordheim tunneling, typically, the source, drain, and substrate are grounded, and the control gate is taken to a potential in a range of approximately 15-20 volts, with a corresponding programming time of approximately 10 milliseconds.
Nanocrystals are being investigated as a replacement to continuous floating gates in nonvolatile memories. These are discontinuous storage elements that overlie a tunnel dielectric. The nanocrystals are not programmed using hot electron injection using the conventional method previously described because too much of the charge would be concentrated in the storage elements closest to the drain. Therefore, direct tunneling of electrons from the conduction band of the substrate to the conduction band of the nanocrystal or of holes from the valence band of the substrate to the valence band of the nanocrystal is typically the process used to program and erase the nanocrystal memory elements.
FIG. 1
includes an illustration of drain current versus drain voltage for an ideal metal oxide semiconductor field-effect transistor (MOSFET) with a constant gate potential. The source and the substrate or well region are grounded. The linear region
12
generally reflects that the current-voltage (I−V) characteristics are linear through that region. The other region, which is the saturation region
14
, is where increasing drain voltage does not significantly increase the drain current. As will be described later, the significance between the linear region
12
and the saturation region
14
will become apparent as operation of a memory cell is described. It should be noted at this point that many of the programming mechanisms used, particularly in hot carrier injection, operate the drain voltage such that the transistor is operating in the saturation region
14
.


REFERENCES:
patent: 5233562 (1993-08-01), Ong et al.
patent: 5457652 (1995-10-01), Brahmbhatt
patent: 5621233 (1997-04-01), Sharma et al.
patent: 192486 (1995-07-01), None
Kim et al., “Room Temperature Single Electron Effects in Si Quantum Dot Memory with Oxide-Nitride Tunneling Dielectrics,” IEEE, 4 pgs. (1998).
Yamada et al., “A Self-Convergence Erasing Scheme for a Simple Stacked Gate Flash EEPROM,” IEEE, pp. 11.4.1-11.4.4 (1991).
Shum et al.; U.S. application No. 09/342,725 filed Jun. 29, 1999.
White et al.; U.S. application No. 09/495,354 filed Feb. 1, 2000.

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