Process for obtaining high-voltage N channel transistors particu

Fishing – trapping – and vermin destroying

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437 43, 437 44, 437 48, 437 52, 437191, H01L 2170

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active

050860089

ABSTRACT:
The process call for N.sup.- doping of a predetermined portion of a type-P semiconductor substrate preceding deposit and definition of a layer of gate polysilicon on a part of said predetermined portion and on an adjacent portion of substrate. After oxidation of the polysilicon there is performed an N.sup.+ doping in the remaining part of said predetermined portion of the substrate and of an additional substrate portion located on the opposite side of the gate.

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Ho et al., "Si/S102 Interface Oxidation Kinetics: A Physical Model for the Influence of High Substrate Doping Levels", J. of Electrochemical Society, Sep. 1979, pp. 1516-1530.
Deal et al., "Thermal Oxidation of Heavily Doped Silicon", J. Electrochemical Soc., Apr. 65, pp. 430-435.

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