Process for multiplying the frequency of a clock signal with con

Details Process for multiplying the frequency of a clock signal with con Process for multiplying the frequency of a clock signal with con

1998-05-22

2000-07-18

Tran, Toan

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Frequency or repetition rate conversion or control

327116, H03B 1900

Patent

active

060912707

ABSTRACT:
A frequency-doubling block includes an input terminal for the incident signal, a first variable delay cell linked to the input, and an EXCLUSIVE OR gate, one input of which is linked to the output of the first delay cell, the other input of which is linked to the input terminal, and the output of which is able to deliver an output clock signal at twice the frequency of the incident signal. A comparison circuit compares the duty ratio of the output signal with a predetermined reference value and a modulation circuit modulates the value of the first delay as a function of the result of the comparison.

REFERENCES:
patent: 4710653 (1987-12-01), Yee
patent: 4799022 (1989-01-01), Skierszkan
patent: 5297179 (1994-03-01), Tatsumi
patent: 5514990 (1996-05-01), Mukaine et al.
patent: 5883534 (1999-03-01), Konodoh et al.

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