Fishing – trapping – and vermin destroying
Patent
1995-05-03
1997-12-23
Graybill, David
Fishing, trapping, and vermin destroying
22818022, H01L 21283, H01L 2158, H01L 2160
Patent
active
057007152
ABSTRACT:
A process for mounting one or more dies a substrate, such as by ball-bumps. In one embodiment, a thin layer of heat-reflective material, such as gold, is disposed over the surface of the die facing the substrate, to shield the substrate from heat generated by the die. Other embodiments are directed to "pillar" spacers formed on the surface of the die and/or the substrate to control the spacing therebetween. The pillars can be thermally-conductive or thermally non-conductive. Thermally-conductive pillars can be thermally isolated from the die or substrate by an insulating layer. Thermally-conductive pillars can be employed to extract heat from selected areas of a die, into selected lines or areas of the substrate, and the heat on the substrate can then be dissipated by a coolant. Lines on the substrate which are advertently heated by the die can be employed to limit the current of selected circuits on the semiconductor die.
REFERENCES:
patent: 3257588 (1966-06-01), Mueller
patent: 3611065 (1971-10-01), Zshauer et al.
patent: 3871015 (1975-03-01), Lim et al.
patent: 3893156 (1975-07-01), Riseman
patent: 4545610 (1985-10-01), Lakritz et al.
patent: 4551747 (1985-11-01), Gilbert et al.
patent: 4600273 (1986-07-01), Ohno
patent: 4878611 (1989-11-01), Lovasco et al.
patent: 4950623 (1990-08-01), Dishon
patent: 5056215 (1991-10-01), Blanton
patent: 5089876 (1992-02-01), Ishioka
patent: 5120678 (1992-06-01), Moore et al.
patent: 5186383 (1993-02-01), Melton et al.
patent: 5283446 (1994-02-01), Tanisawa
patent: 5284796 (1994-02-01), Nakanishi et al.
patent: 5341564 (1994-08-01), Akhauain et al.
patent: 5400950 (1995-03-01), Meters et al.
"Area Array Substrate-To-Carrier Interconnection Using Corner Standoff", IBM T.D.B., vol. 24, No. 11, Apr. 1987, pp. 4736-4737.
"Pin Support For IC Chip To Prevent C4 Collapse During Reflow", IBM T.D.B., vol. 30, No. 11, Apr. 1988. pp. 320-321.
Graybill David
LSI Logic Corporation
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