Coating processes – Direct application of electrical – magnetic – wave – or... – Pretreatment of substrate or post-treatment of coated substrate
Patent
1991-08-08
1994-03-08
Beck, Shrive
Coating processes
Direct application of electrical, magnetic, wave, or...
Pretreatment of substrate or post-treatment of coated substrate
427534, 427 96, 427 98, 427 99, 427123, 427124, 427125, 427250, 427252, 437186, 437187, 437189, 437192, 437195, 437229, 437231, B05D 512, C23C 1606, H01L 21314
Patent
active
052925587
ABSTRACT:
A method for forming interconnections in microelectronic devices, including interconnections through small vias between different layers in the microelectronic devices include the spin coating of a film comprising a polyoxometalate and an organic material on the substrate. The film is optionally patterned by lithography, the polymer is removed, and the polyoxometalate is reduced to a metal layer. The metal layer may in one embodiment provide a nucleating zone for the deposition of metal.
REFERENCES:
patent: 4694138 (1987-09-01), Oodaira et al.
patent: 4843034 (1989-06-01), Herndon et al.
patent: 4865873 (1989-09-01), Cole, Jr. et al.
patent: 4914052 (1990-04-01), Kanai
patent: 5026666 (1991-06-01), Hills et al.
patent: 5087589 (1992-02-01), Chapman et al.
Hopper, R. T., "How to Apply Noble Metals to Ceramics"; Ceramic Industry, Jun. 1963 (no pp. numbers).
Lee, Pei-Ing et al. "Chemical Vapor Deposition of Tungsten (CVD W) as Submicron Interconnection and Via Stud"; J. Electrochem. Soc., vol. 136, No. 7, Jul. 1989, pp. 2108-2112.
Creighton, "A Mechanism for Selectivity Loss During Tungsten CVD" Jan. 1989, J. Electrochem. Soc. pp. 271-276.
Ting et al. "Selective Electroless Metal Deposition for Via Hole Filling in VLSI Multilevel Interconnection Structures" Feb. 1989, J. Electrochem. Soc. 462-466.
van de Putten et al. "Selective Electroless Ni Depositio On Si for Contact Hole Filling", Oct. 1989, Abstract 467 ECS Fall Meeting.
Flis et al, "Nucleation and Growth of Electroless Nickel Deposits On Molybdenum Activated with Palladium" Jan. 1984, J. Electrochem. Soc. pp. 51-57.
Harada et al, "The Characterization of Via-Filling Technology with Electroless Plating Method" Nov. 1986, J. Electrochem. pp. 2428-2430.
Pai et al. "A Low Temperature Copper Deposition Process for Interconnection Application", Oct. 1989, Abstract 212 ECS Fall Meeting.
Lami et al. "Evaluation of the Selective Tungsten Deposition Process for VLSI Circuit Applications" Apr. 1988, J. Electrochem. Soc. 980-984.
Argitis Panagiotis
Carls Joseph C.
Heller Adam
Beck Shrive
Chen Bret
Freedman Irving M.
University of Texas at Austin, Texas
LandOfFree
Process for metal deposition for microelectronic interconnection does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Process for metal deposition for microelectronic interconnection, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Process for metal deposition for microelectronic interconnection will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-151866