Pulse or digital communications – Testing – Phase error or phase jitter
Patent
1997-05-29
1999-07-13
Chin, Stephen
Pulse or digital communications
Testing
Phase error or phase jitter
375226, 375371, H04B 346
Patent
active
059237066
DESCRIPTION:
BRIEF SUMMARY
FIELD OF THE INVENTION
The present invention relates to a process for measuring the phase jitter of a data signal by means of a phase demodulator using a predetermined clock signal.
BACKGROUND INFORMATION
A process for measuring the phase jitter of a data signal is described in the IEE publication "International Conference on Measurements for Telecommunication Transmission Systems--MTTS" vol. 85 (1985) pages 173 and 174. In this known process, a predetermined clock signal is used as a reference signal which is compared with a data signal with regard to phase relation to determine the phase jitter of the data signal. Problems occur with this known process due to static phase shifts that cause a reduction in dynamic range. In addition, high-frequency components occur with regard to the baseband of the resulting jitter signal, thereby requiring a low-pass filter to eliminate the high-frequency components.
As described in the aforementioned publication, amplitude-modulated pulses can be obtained within the scope of the phase jitter measurement by sampling a ramp-like signal coupled to the clock signal when a data signal occurs. This known process apparently does not use a phase comparator connected to a predetermined clock signal via a frequency divider and a gate circuit controlled by a control circuit.
Furthermore, German Patent No. 38 33 486 C1 describes a process and a circuit arrangement for measuring the phase jitter of a data signal in which a ramp-like signal-generating integrator with a downstream sample-and-hold circuit is used. In this known process, the integrator is released to generate the ramp-like signal when an upstream release circuit supplies an output signal. This output signal is generated as a function of the occurrence of a clock signal and the starting status of a digital comparator which is downstream from an arrangement with two detent memories and a detent counter that receives the clock signal. The detent memories receive pulses derived from the data signals in parallel. The output of the digital comparator is connected to an address generator with a downstream intermediate memory and a downstream digital-to-analog converter. An approximate phase jitter value appears at the output of the digital-to-analog converter. A precision phase jitter value is obtained at the output of the sample-and-hold circuit. A measured quantity representing the phase jitter is generated from these two values by means of a summation circuit.
SUMMARY OF THE INVENTION
An object of the present invention is to provide an improved process for measuring phase jitter which yields accurate measurement results with comparatively little expense.
In a process for measuring the phase jitter of a data signal using a predetermined clock signal by means of a phase modulator, the aforementioned object is achieved by deriving an auxiliary clock signal from a predetermined clock signal with the help of a gate circuit, where the frequency of the auxiliary clock signal corresponds to the frequency of the data signal. The phase difference between the data signal and the auxiliary clock signal is determined, and when the phase deviation found between the data signal and the auxiliary clock signal exceeds a predetermined phase deviation, the gate circuit is actuated, generating a modified clock signal, such that the phase deviation drops below the predetermined deviation. A comparison clock signal is then formed from the modified auxiliary clock signal so that the comparison clock signal has a phase relation to the modified clock signal such that with a phase demodulator receiving at its input the comparison clock signal and the data signal and having a ramp-like signal-generating integrator and a downstream sample-and-hold circuit, an edge of the corresponding pulse of the data signal falls in the middle of the ramp-like signal when the phase jitter is zero. The data signal and the comparison clock signal are then sent to the phase demodulator to measure the phase jitter, where the integrator is actuated by the comparis
REFERENCES:
patent: 3671776 (1972-06-01), Houston
patent: 4819080 (1989-04-01), Cucchietti et al.
patent: 4974234 (1990-11-01), Brandt
Chin Stephen
Lenihan Thomas F.
Liu Shuwang
Mayer Richard L.
Tektronix Inc.
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