Process for manufacturing three dimensional IC's

Details Process for manufacturing three dimensional IC's Process for manufacturing three dimensional IC's

1992-09-30

1993-11-30

Hearn, Brian E.

Fishing, trapping, and vermin destroying

437915, 437924, 148DIG12, H01L 2172

Patent

active

052665119

ABSTRACT:
A first semiconductor substrate comprises an integrated circuit formed therein and an alignment mark formed thereon. The top surface of the first semiconductor substrate is covered with a first insulating layer and is planarized. The alignment mark is formed in a space between a plurality of groups of elements, such as a scribe line area. A second semiconductor substrate is provided with a groove corresponding to said space, or scribe line area, and a second insulating layer is formed on thereon and so as to bury the groove, and the exposed surface of the second insulating layer is planarized. The two planarized surfaces of the first and second semiconductor substrates are positioned in facing, contiguous relationship and are bonded to each other, while an infra-red microscope is used for alignment of the space and the groove. The back surface of the second semiconductor substrate is selectively etched until the second insulating layer, as filed in the groove, is exposed. A second integrated circuit is formed in the second semiconductor substrate at a position therein determined by detecting the alignment mark on the first semiconductor substrate through a visible ray microscope.

REFERENCES:
patent: 4789214 (1988-12-01), Vilhelmsson et al.
patent: 4902637 (1990-02-01), Kondou et al.
patent: 5075253 (1991-12-01), Sliwa
patent: 5087585 (1992-02-01), Hayashi

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