Semiconductor device manufacturing: process – Packaging or treatment of packaged semiconductor – Assembly of plural semiconductive substrates each possessing...
Patent
1997-02-21
2000-02-08
Graybill, David E.
Semiconductor device manufacturing: process
Packaging or treatment of packaged semiconductor
Assembly of plural semiconductive substrates each possessing...
438612, 438613, 438614, 438615, 438617, 438667, 438675, H01L 2160
Patent
active
060227583
DESCRIPTION:
BRIEF SUMMARY
FIELD OF THE INVENTION
The present invention relates to integrated circuits generally and more particularly to packaged integrated circuits.
BACKGROUND OF THE INVENTION
There are known a great variety of integrated circuits and integrated circuit packaging designs. Published PCT Patent Application PCT/EP92/02134, filed Sep. 14, 1992 which has matured into U.S. patent application Ser. No. 962,222, the disclosure of which is hereby incorporated by reference, of the present assignee describes a particularly advantageous integrated circuit package.
An article entitled "Flip Chips Improve Hybrid Capability by Robert LeFort et al in Hybrid Circuit Technology, May 1990 pp. 44-46 describes packaged integrated circuits known as Flip Chips, which are formed with a multiplicity of solder bumps on a planar surface thereof for flat mounting onto a circuit board.
It has been proposed in Electronic Packaging & Production, May 1992 at pages 25 and 26 to mount a Flip Chip onto a ball-grid array having a fan-out of conductors, extending through plated through apertures, and leading to an array of solder bumps.
SUMMARY OF THE INVENTION
The present invention seeks to provide an improved packaged integrated circuit.
There is thus provided in accordance with a preferred embodiment of the present invention a packaged integrated circuit including: plurality of pads; one packaging layer; and plurality of pads to individual ones of solder leads.
Preferably, the electrical connections extend transversely to the package layer.
In accordance with a preferred embodiment of the present invention, the electrical connections are formed by conventional metal deposition and plating techniques following attachment of the packaging layer to the substrate.
There is also provided in accordance with a preferred embodiment of the present invention a method of forming a packaged integrated circuit comprising: plurality of pads; one packaging layer; and plurality of pads to individual ones of solder leads.
In accordance with a preferred embodiment of the present invention, the electrical connections are formed by conventional metal deposition and plating techniques following attachment of the packaging layer to the substrate.
The foregoing steps may be carried out waferwise or diewise.
BRIEF DESCRIPTION OF THE DRAWINGS
The present invention will be understood and appreciated more fully from the following detailed description, taken in conjunction with the drawings in which:
FIG. 1A is a partially cut away simplified illustration of an integrated circuit package constructed in accordance with a preferred embodiment of the present invention;
FIG. 1B is a partial sectional simplified illustration of the internal structure of the integrated circuit package shown in FIG. 1A;
FIGS. 2A-2G are sectional illustrations of the steps of a preferred method of waferwise manufacture of the integrated circuit package of FIGS. 1A and 1B;
FIGS. 3A-3G are sectional illustrations of the steps of another preferred method of waferwise manufacture of the integrated circuit package of FIGS. 1A and 1B;
FIGS. 4A and 4B are illustrations of certain steps in a preferred method of non-waferwise manufacture of the integrated circuit package of FIGS. 1A and 1B;
FIGS. 5A and 5B are illustrations of certain steps in another preferred method of non-waferwise manufacture of the integrated circuit package of FIGS. 1A and 1B;
FIG. 6 is a simplified illustration of a finished integrated circuit package constructed and operative in accordance with another embodiment of the present invention;
FIGS. 7A and 7B are simplified partially cut away illustrations of a partially completed integrated circuit package of the type shown in FIG. 6, in accordance with two alternative embodiments of the present invention;
FIGS. 8A-8C illustrate three stages in the manufacture of an integrated circuit package in accordance with one embodiment of the present invention;
FIGS. 9A and 9B illustrate two stages in the manufacture of an integrated circuit package in accordance with another embodiment
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R. Lefort, et al., Flip Chips Imrove Hybrid Capability, Hybrid Circuit Technology, pp. 44-46, May 1990.
Sonic-Mill Processing, Albuquerque, New Mexico, Brochure. Date Not Available.
G. Messner, et al., Multichip Modules, Technical Monograph of the Int'l Society for Hybrid Microelectronics, pp. 68-70. Date Not Available.
Packaging Ideas, Electronic Packaging and Production, Edited by Howard Markstein, May 1992, pp. 25-26.
Graybill David E.
Shellcase Ltd.
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