Semiconductor device manufacturing: process – Formation of electrically isolated lateral semiconductive... – Grooved and refilled with deposited dielectric material
Reexamination Certificate
2000-04-28
2002-06-25
Niebling, John F. (Department: 2812)
Semiconductor device manufacturing: process
Formation of electrically isolated lateral semiconductive...
Grooved and refilled with deposited dielectric material
C438S442000, C438S607000
Reexamination Certificate
active
06410404
ABSTRACT:
TECHNICAL FIELD
This invention relates to a process for manufacturing integrated circuit structures of the SOI type, and more specifically, this invention concerns a process for manufacturing SOI power and control circuit structures integrated on a semiconductor substrate having a first type of conductivity.
BACKGROUND OF THE INVENTION
Integrated circuit structures having a Silicon-On-Insulator (SOI) type are formed on insulating substrates, and used to form MOS and CMOS devices having a strong decoupling from the substrate and a vertical insulation from one another.
Several prior art processes exist for forming SOI integrated circuit structures. For example, SOI substrates have been formed by bonding a first substrate, which is covered with an oxide layer, onto a second substrate, so that the oxide layer is sandwiched between the first and second substrates. The joining of the substrates is achieved by a bonding process to silicon which has problems of yield and is only used for high “added value” integrated circuits.
Another prior art process subjects the substrate to implantation with O
2
at a very heavy dosage, thereby forming a buried oxide layer. However, this process is cost intensive.
More recent is a proposal for forming SOI substrates from an insulating layer whereon a layer of monocrystalline silicon is grown epitaxially. The epitaxial layer of monocrystalline silicon will later host MOS and CMOS devices. However, growing a substantial epitaxial layer over the surface of the insulating layer has also proved to be fairly critical.
There has yet to be developed a process for manufacturing SOI integrated circuit structures which have such structural and functional features as to manufacture MOS and CMOS devices economically and overcome the drawbacks that still beset prior SOI integrated circuit structures.
SUMMARY OF THE INVENTION
Embodiments of the invention form, on the same semiconductor substrate, both SOI integrated circuit structures, and traditional structures.
Presented is a process for forming at least one well with a second type of conductivity in a semiconductor substrate having a first type conductivity, and forming a hole in the well or wells. The hole is coated with an insulating layer and an opening formed therein at the bottom of the hole. Later, the hole is filled with an epitaxial layer grown from a seed accessible through the opening in the hole.
The features and advantages of a device according to the invention will become clear from the following description of an embodiment thereof, given by way of example and not of limitation with reference to the accompanying drawings. Additionally, although this inventive process is described with reference to a structure comprising both power and control devices, this description is only made for convenience of explanation, and in no way limits the scope of the invention to those devices.
REFERENCES:
patent: 4473598 (1984-09-01), Ephrath et al.
patent: 4654958 (1987-04-01), Baerg et al.
patent: 5422299 (1995-06-01), Neudeck et al.
patent: 5457338 (1995-10-01), Borel
patent: 5904535 (1999-05-01), Lee
patent: 6140196 (2000-10-01), Tung
patent: 0295786 (1988-12-01), None
patent: 402066947 (1990-03-01), None
Gilbert et al., “Quasi-Dielectrically Isolated Bipolar Junction Transistor with Sub-Collector Fabricated Using Silicon Selective Epitaxy,”IEEE, pp. 199-202, 1991.
Iannucci Robert
Jorgenson Lisa K.
Niebling John F.
Seed IP Law Group PLLC
Simkovic Viktor
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