Semiconductor device manufacturing: process – Making passive device – Trench capacitor
Reexamination Certificate
2002-02-01
2004-05-11
Zarneke, David A. (Department: 2829)
Semiconductor device manufacturing: process
Making passive device
Trench capacitor
Reexamination Certificate
active
06734078
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates in general to a method for manufacturing semiconductors with a trench capacitor. In particular, the method prevents gaps between the conductive layers of the trench capacitor to form a trench capacitor with good conductivity.
2. Description of the Related Art
FIG. 1A
shows a trench having a predetermined depth formed in a predetermined location on a semiconductor substrate. The trench
10
of a predetermined depth is formed in a semiconductor substrate
1
, such as silicon semiconductor, using a photo mask
2
.
FIG. 1B
shows a fiberglass film
11
of an n+ type doping at the bottom of the trench
10
. The fiberglass film
11
is typically formed with doped arsenic (As), thus briefed as ASG. After annealing. As is diffused into the semiconductor substrate
1
to form a buried plate
12
as the region enclosed by the dotted line in FIG.
1
C. The fiberglass film
11
is removed after the buried plate
12
is formed. Next, as shown in
FIG. 1D
, a dielectric layer
13
is formed at the bottom of the trench
10
. In
FIG. 1E
, a heavily doped first polysilicon layer
14
is formed at the bottom region of the trench. The first polysilicon layer
14
, the dielectric layer
13
and the buried plate
12
form a trench capacitor with the first polysilicon layer
14
and the buried plate
12
being the electrodes. An insulating layer is deposited at the upper part of the trench
10
to form a collar insulating layer
15
after dry etching, exposing the first polysilicon layer
14
as shown in FIG.
1
F. The collar insulating layer
15
is a sidewall gradually thinning at the top as a result of etching. The collar insulating layer
15
can be formed with Tetra Ethyl Oxysilane. A second polysilicon layer
16
is then formed at the upper part of the trench
10
as shown in FIG.
1
G. The second polysilicon layer
16
is in contact with the first polysilicon layer
14
and lower than the depth of the trench
10
. The collar
16
on the sidewall is wet etched to form a diffusion indentation
17
; whereupon the diffusion indentation is narrows from the bottom up as shown in FIG.
1
H. Finally, a buried strap
18
is formed in the trench
10
as shown in FIG.
1
I and the trench capacitor is formed in the semiconductor accordingly.
As semiconductor technology advances into sub-micron technologies, the electrical connection between the conductive layers is sometimes incomplete. As shown in
FIG. 2
, the collar insulating layer
15
formed by wet etching in the trench
10
is not always perpendicular to the first polysilicon layer
14
. Therefore, the formation of the buried strap
18
in the trench
10
causes some gaps
19
to form in the diffusion indentation
17
. The dopant in the first polysilicon layer
14
penetrates to the semiconductor substrate
1
through the second polysilicon layer
16
and the buried strap
18
of the diffusion indentation
17
to form a capacitor connection diffusion
20
with other components, such as transistors. However, if the buried strap
18
does not fill the diffusion indentation
17
up thoroughly causing some gaps
19
to be generated, the dopant in the first polysilicon layer
14
cannot diffuse to the semiconductor substrate
1
causing an increase in the resistance and a decrease in the yield.
SUMMARY OF THE INVENTION
An object of the present invention is to provide a semiconductor with a trench capacitor with good electrical connection between the conductive layers. The semiconductor comprises a buried plate formed on the U-shaped sidewall of the trench capacitor, a U-shaped dielectric layer formed in a lower region of the trench capacitor, a first conductive layer formed on the dielectric layer in the lower region, a collar insulating layer having a predetermined depth formed on the sidewall of a collar region of the trench capacitor, a second conductive layer having a predetermined depth formed on the collar insulating layer, and a buried strap formed on the first conductive layer, in contact with the sidewall of the trench capacitor, the collar insulating layer and the collar conductive layer.
Another object of the present invention is to provide a method for manufacturing semiconductors with trench capacitors having a low-resistance buried strap. The method comprises the steps of providing a substrate, forming a trench in the substrate, forming a glass doping layer with a first predetermined depth at the bottom of the trench, wherein the glass doping layer is doped with an n-type dopant, forming a first dielectric layer covering the glass doping layer in the trench, diffusing the n-type dopant of the glass doping layer to the substrate by annealing to form a buried plate, removing the first dielectric layer and the glass doping layer, sequentially forming a second dielectric layer and a first conductive layer having depths approximately equal to the first predetermined depth in the trench, wherein the region above the first conductive region is defined as the collar region, forming a U-shaped insulating layer in the collar region, forming a collar conductive layer at the bottom of the U-shaped insulation layer in the collar region, removing the U-shaped insulating layer not in contact with the collar conductive layer to form a collar insulating layer, and forming the buried strap in the trench.
One feature of the present invention lies in the provision of the collar insulating layer on the sidewall of the collar region in the trench capacitor.
Another feature of the present invention lies in the electrical connection between the buried strap and the first conductive layer in the collar region of the trench capacitor.
Yet another feature of the present invention is the formation of the trench capacitor in the substrate of the semiconductor memory.
The other feature of the present invention is the collar insulating layer being equal to or lower than the collar conductive layer.
With the formation of the diffusion indentation of a suitable shape, no gap is formed from the deposition of the buried strap in the diffusion indentation.
REFERENCES:
patent: 6372573 (2002-04-01), Aoki et al.
Harrison Monica D.
Ladas & Parry
Winbond Electronics Corp.
Zarneke David A.
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