Process for manufacturing semiconductor package and circuit...

Details Process for manufacturing semiconductor package and circuit... Process for manufacturing semiconductor package and circuit...

1998-12-02

2002-04-02

Bowers, Charles (Department: 2813)

Semiconductor device manufacturing: process

Packaging or treatment of packaged semiconductor

Including adhesive bonding step

C438S113000, C438S464000

Reexamination Certificate

active

06365438

ABSTRACT:

TECHNICAL FIELD
The present invention relates to a manufacturing process for a small-sized and thin type semiconductor package. More particularly, to a manufacturing process for a semiconductor package by which an circuit substrate will not be wasted and which allows a plurality of packages to be taken from the substrate thereby having the highly productivity and to an circuit substrate aggregation or assembly used for manufacturing such packages.
BACKGROUND TECHNOLOGY
As a semiconductor package becomes smaller and more integrated, the flip-chip bonding method has been developed wherein a bare chip is directly mounted on a substrate with its face directed downward. More recently, a variety of portable tools such as a VTR having a camera integrated thereinto and a personal handy telephone is appearing into the market one after another and such a portable tool has a package as small as a bare chip integrated therein, namely a chip size/scale package (CSP). Because of such a situation, CSP's are strongly needed in the market, thereby the development of CSP's recently is under accelerating.
In manufacturing circuit board aggregation or assembly
100
at a manufacturer's site, a roll of 1 m wide glass filler sheet having a resin impregnated thereinto is cut in accordance with a standard size of 1 m×1 m or 1 m×1.2 m. Then, a copper film is laminated onto the both sides of the standardized sheet, which will be pressed into an original substrate. The original substrate is further cut into substrate materials with a convenient and readily usable size.
In
FIG. 20
, a plan view of substrate material
110
is shown. This substrate material is obtained by cutting an original sheet with a standard size into nine pieces. Substrate material 110 measures 330 mm wide (W) and 330 mm long (L). For example, ten (10) strips of circuit board aggregation
100
will be obtained by cutting this substrate material
110
. Each circuit substrate aggregation is, for example, 56 mm wide (W
1
) and 115 mm long (L
1
). Each circuit substrate aggregation
100
is, as illustrated in
FIG. 20
, arranged as two vertical rows X and five horizontal columns.
In
FIG. 21
, an example of circuit substrate aggregation
100
is shown. The circuit substrate aggregation has a blank area (margins) for manufacturing packages along the perimeter. In particular, the substrate has a b
1
wide (for example 5 mm) manufacturing blank area along the vertical perimeter and b
2
wide (for example 7 mm) manufacturing blank area along the horizontal perimeter.
In the area surrounded by the manufacturing blank area of the circuit substrate aggregation
100
, cut lines
2
are formed in the X and Y directions which are perpendicular to each other so as to form a plurality of individual circuit substrate
1
to be obtained by cutting it. From circuit substrate aggregation
100
as shown in
FIG. 21
, fifty-five (=5×11) circuit substrates having the size of 9 mm×9 mm can be obtained.
A conventional manufacturing process for CSP type semiconductor packages will now be briefly explained by referring to
FIGS. 22A
to
23
C′. In
FIGS. 22A-22C
and
FIGS. 23A-23C
, respectively, top plan views are shown in the right side of the figures while cross-sectional views obtained by cutting the top plan views along the cutting lines are shown in the left side. In the example of
FIGS. 22A
to
23
C′, four circuit substrates are illustrated to be taken.
A conventional process for manufacturing semiconductor packages includes the steps for forming a circuit substrate (FIG.
22
A′), mounting IC chips onto the substrate (FIG.
22
B′), encapsulating the mounted chips with resin (FIG.
22
C′), attaching standard member on the encapsulated (sealing) chips (FIG.
23
A′), dicing the chips (FIG.
23
B′) and forming electrodes on the chips (FIG.
23
C′).
In manufacturing semiconductor packages, through-holes (not shown) are formed on the circuit substrate aggregation
100
, both surfaces of which are copper laminated in the step of forming the circuit substrate.
Then, on the both surfaces of this circuit substrate aggregation
100
, copper-plated layers are formed by means of electroless copper plating and electro copper plating. Further, the copper-plated layers are laminated with etching resist, which will be sequentially exposed to light and developed to form pattern masks. Thereafter, the copper-plated layers are subjected to pattern etching via the pattern masks by using etching solution. Through this pattern etching process, several sets of IC connecting electrodes (bonding pattern)
3
for a plurality of chips are formed on the upper surface of circuit substrate aggregation
100
and external connection electrodes
4
, which are pad electrodes arranged in a matrix, are formed on the bottom side, respectively.
Next, a solder resist processing follows, thereby forming a resist film on the bottom side of circuit substrate aggregation
100
. This resist film has openings where external connection electrodes
4
, which are the solderable region, are exposed. By forming this resist film in this way, the bottom surface of integrated surface
100
will be planarized. Thus, the circuit substrate aggregation is completed wherein a number of same-shaped platable regions are arranged on the bottom surface in a matrix manner (FIGS.
22
A and
22
A′).
In the next step of mounting the IC chips on the substrate, solder bumps
5
are formed on the pad electrode of the IC wafer (not shown). The process for forming solder bumps
5
includes the stud bump method, ball bump method and plated bump method. The plated bump method among these is suitable for miniaturizing the IC chips because it allows the bumps to be formed in a narrow space between the pad electrodes.
Then, the IC wafer on which the solder bumps are formed is cut into chips of a predetermined size while being attached on a adhesive tape, to thereby form the IC chips
6
. In this cutting process, the full-cut scheme is employed in cutting the wafer in the X and Y directions with an apparatus such as a dicing saw. After the wafer is cut, IC chips
6
on the adhesive tape are separated into a plurality of individual units.
Next, flux (not shown) is applied onto a predetermined location of either the solder bumps of the divided IC chips or IC connecting electrodes
3
formed on the upper surface of circuit substrate aggregation
100
. When this is completed, IC chips
6
are mounted on the main surface of circuit board aggregation
100
in such a manner that one chip is mounted on a single circuit substrate. The surface of IC chip
6
on which solder bumps
5
are formed is opposed against the upper side of the circuit substrate aggregation and solder bumps
5
are positioned on IC connecting electrodes
3
. Then, IC connecting electrodes
3
are electrically connected to IC chips
6
by means of a solder reflow processing. As described above, IC chips
6
(flip-chips) are mounted onto circuit board aggregation
100
(FIGS.
22
B and
22
B′).
In the next encapsulation step, a plurality of IC chips
6
is integrally encapsulated using a thermosetting resin
7
by performing a side-potting across the adjacent IC chips
6
. In such a manner, the same IC chips
6
are secured on each circuit substrate
1
of the circuit substrate aggregation
100
with the face down direction as shown in FIGS.
22
C and
22
C′.
In the next step of attaching a standard member, the planar bottom surface of the circuit substrate aggregation on which the IC chips are mounted is attached to standard member
8
by using a adhesive or a PSA (pressure-sensitive adhesive) tape. The adhesion between circuit substrate aggregation
100
and standard member
8
is secured because both of the attached surfaces are planar (FIGS.
23
A and
23
A′).
In the next dicing step, as shown in FIGS.
23
B and
24
B′, circuit substrate aggregation
100
is cut with a cutting device such as a dicing saw along the cut lines formed on the

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