Process for manufacturing semiconductor integrated circuit devic

Details Process for manufacturing semiconductor integrated circuit devic Process for manufacturing semiconductor integrated circuit devic

1991-07-18

1993-05-11

Hearn, Brian E.

Fishing, trapping, and vermin destroying

437190, 437194, 437195, 437209, H01L 2166, H01L 21304

Patent

active

052100413

ABSTRACT:
A wafer manufacturing process for a semiconductor integrated circuit device, including testing the semiconductor wafer at a unit of chip each time a predetermined treating step is performed. The test results are feed to a computer control for restricting succeeding treatments or further testing of chip or chips based on the test results and the predetermined number of chips to be produced. Semiconductor wafer(s) is/are loaded for manufacture on the basis of the number of chips to be produced, taking into account of any losses created by defective chips detected during each testing step and any excess created by additional semiconductor wafers loaded in response to shortages created by defects. The excess chips are monitored by the computer control and any succeeding treatments or further testing of the excess chips are halted to save time and manufacturing costs.

REFERENCES:
patent: 4607219 (1986-08-01), Isosaka
patent: 4731855 (1988-03-01), Suda et al.
patent: 4740079 (1988-04-01), Koizumi et al.
patent: 4777146 (1988-10-01), Bylsma et al.
patent: 4918377 (1990-04-01), Buehler et al.
patent: 4985988 (1991-01-01), Littlebury
patent: 5047711 (1991-09-01), Smith et al.
Semiconductor Fabrication in the Age of the 0.8 to 0.5-.mu.m Process, pp. 1-12 (English), pp. 35-40 (Japanese), issued on Nov. 2, 1989 by Press Journal.
Laboratory and Factory Automation for VLSI Development and Mass Production (invited) pp. 736-739, issued in Aug. 1988 IEDM.

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