Process for manufacturing semiconductor integrated circuit...

Details Process for manufacturing semiconductor integrated circuit... Process for manufacturing semiconductor integrated circuit...

2003-02-21

2004-10-05

Lebentritt, Michael S. (Department: 2824)

Semiconductor device manufacturing: process

Chemical etching

Combined with the removal of material by nonchemical means

C438S694000, C438S696000, C438S740000

Reexamination Certificate

active

06800557

ABSTRACT:

BACKGROUND OF THE INVENTION
The present invention relates to a technique for manufacturing a semiconductor integrated circuit device and, more particularly, to a technique which is effective in achieving anticorrosion of metal wirings formed by a chemical mechanical polishing (CMP) method.
Japanese Patent Laid-open No. 135192/1995 (hereinafter referred to as “Hayakawa”) has disclosed a post-polishing method which makes it possible to lower the particle level after polishing treatment on a wafer by performing, without drying the wafer, a series of steps including chemical mechanical polishing, followed by wafer inverting standby, physical cleaning, chemical-cleaning (or spin-cleaning) and rinsing treatments. In the polishing apparatus to be used in this process, a wafer mounting portion in the polishing unit is made to have a construction which is capable of keeping the wafer wet, and an inter-unit wet conveying mechanism is used for conveying wafers among a polishing unit, a cleaning unit and a rinsing/drying unit, whereas an in-unit wet conveying mechanism is used for conveying wafers between the individual cleaning chambers in the cleaning unit.
A CMP apparatus for an oxide film comprising a wafer feeding portion, a polishing portion, a wafer extracting portion and a dress unit is disclosed on pp. 53 to 55 of Electronic Materials, issued in May, 1996, by the Association of Industrial Researches (hereinafter referred to as “Ohmura et al.”). In this apparatus, the wafer is conveyed by a conveyor robot from a load cassette to a polishing portion and is polished. The polished wafer is then scrub-cleaned on its front and back sides with pure water, is stocked in an unload cassette, and thereafter, is stocked in water.
On pp. 62 to 65 of Electronic Materials, issued in May, 1996 (hereinafter referred to as “Tsujimura et al.”), there is disclosed a technique for the transfer of a wafer in an underwater stock from a polishing step to a post-cleaning treatment (aiming at removing undesired particles such as abrasive grains introduced at the polishing time from the wafer surface and generally conducted before the wafer surface is naturally dried).
On pp. 33 to 35 of Electronic Materials, issued in May, 1996 (hereinafter referred to as “Hirakura”), there is disclosed a CMP apparatus comprising a polishing disc (or platen) for performing a primary polishing treatment, a polishing disc for performing a second polishing (or buff polishing) treatment, a cleaning station for cleaning the polished wafer with water and a brush, and an unloader for stocking the wafer in a submerged state.
Japanese Patent Laid-open No. 64594/1996 (hereinafter referred to as “Shibuki”) has disclosed a metal CMP process using a slurry containing an anticorrosive agent, such as BTA, so as to prevent corrosion of the metal, which might otherwise occur in the metal CMP process.
SUMMARY OF THE INVENTION
Hitherto, the metal wirings of an LSI have been formed by a process of depositing a metal film, such as an aluminum (Al) alloy film or a tungsten (W) film, over a silicon substrate (or wafer) using a sputtering method and then patterning the metal film by a dry etching method using a photoresist film as a mask.
As the integration of an LSI has become higher in recent years, however, the aforementioned process has become more critical with respect to the wiring resistance due to the finer thickness of the wiring width required by the high integration, producing a higher factor to deteriorate the performance of a logic LSI which requires an especially high performance. Therefore, recently attention has been given to wirings using copper (Cu), which has an electric resistance of about one half of that of Al alloy and an electromigration resistance higher by about one figure than that of Al alloy.
However, Cu is so low in the vapor pressure of its halide as to make it difficult to form the wirings using the dry etching treatment of the related art. Because of this difficulty, there has been introduced a wiring forming process (the so-called damascene process) by which grooves are formed in advance in the insulating film over the silicon substrate, and the Cu film is deposited over the insulating film including the insides of the grooves and any unnecessary Cu film outside the grooves is then polished back by chemical mechanical polishing (CMP) while leaving the Cu film in the grooves.
When the Cu film is polished by the CMP method, however, a portion of the Cu may be eluted by the action of an oxidizing agent added to the polishing slurry, so that a portion of the Cu wirings is corroded, thereby bringing about open defects or short-circuit defects.
This corrosion of the Cu wirings characteristically occurs in the Cu wirings which are connected with the p-type diffusion layer of a pn junction (e.g., a diffusion resistance element, the source and drain of an MOS transistor, or the collector, base and emitter of a bipolar transistor) formed in the silicon substrate. Further, when the metal wirings are formed by polishing another metal material (e.g., W or an Al alloy) by the CMP method or when metal materials (or plugs) are buried in through holes for connecting upper and lower wirings, although not so serious as in the case of Cu wirings, corrosion may be caused for the aforementioned reasons if those metal wirings or plugs are connected with the pn junction.
FIG.
14
(
a
) is a model diagram illustrating an electromotive force generating mechanism of the pn junction; FIG.
14
(
b
) is a graph illustrating the I-V characteristics of the pn junction at a light irradiation time and at a dark time; and
FIG. 15
is a model diagram illustrating a corrosion occurring mechanism of the Cu wirings.
When light comes into the pn junction formed in the silicon substrate, as shown in FIG.
14
(
a
), an external voltage (up to 0.6 V) at + on the p-side and at − on the n-side is generated by the photovoltaic effect of silicon, so that the I-V characteristics of the pn junction are shifted, as illustrated in FIG.
14
(
b
). As a result, a short-circuit current flows, as illustrated in
FIG. 15
, through a closed circuit which is formed of a Cu wiring connected with the p-side (or + side) of the pn junction—the pn junction—the Cu wiring connected with the n-side (or − side) of the pn junction—the polishing slurry which has stuck to the wafer surface, so that the Cu
2+
ions are dissociated from the surface of the Cu wiring connected with the p-side (or + side) of the pn junction, thereby to cause electrochemical corrosion (or electrolytic corrosion).
FIG. 16
is a graph showing relations, which occur at a time a voltage is applied, between a slurry concentration (%) and a Cu etching (eluting) rate. For a slurry concentration of 100%, as seen from
FIG. 16
, the eluting rate of Cu is relatively low, but abruptly rises when the polishing slurry is diluted to some extent with water. It can be said from the foregoing discussion that, when light comes in a pn junction in a case where some of the polishing slurry or its aqueous solution has stuck to the surface of the silicon wafer, the elution of Cu grows prominent to cause electrolytic corrosion. Concretely, when light comes in the surface of the wafer either in the course of conveyance from the polishing step to the post-cleaning step or at a standby time, electrolytic corrosion occurs in the Cu wirings connected with the p-type diffusion layer of the pn junction.
An object of the present invention is to provide a technique which is capable of preventing the corrosion of metal wirings formed by using the CMP method.
This and other objects and various novel features of the invention will become apparent from the following description when taken in conjunction with the accompanying drawings.
A representative aspect of the invention to be disclosed herein will be briefly described in the following.
A process for manufacturing a semiconductor integrated circuit device according to the invention comprises the steps of: forming metal wirings by forming a metal layer

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