Process for manufacturing semiconductor devices by implantation

Details Process for manufacturing semiconductor devices by implantation Process for manufacturing semiconductor devices by implantation

1987-02-17

1988-09-13

Ozaki, George T.

Fishing, trapping, and vermin destroying

437 31, 437152, 437161, 437 28, H01L 21385, H01L 21425

Patent

active

047710098

DESCRIPTION:

BRIEF SUMMARY
DESCRIPTION

1. Technical Field
The present invention relates to a process for manufacturing semiconductor devices which permits the elimination of impurity atoms such as heavy metals present in semiconductor substrates to be used for the formation of semiconductor devices and the gettering of very fine defects.
2. Background Art
So far the above gettering has been performed by the following procedures in a conventional process for manufacturing a semiconductor device, as shown in, e.g., FIGS. 1A to 1E. As shown in FIG. 1A, both main surfaces of, e.g., a p-type silicon substrate 1 are thermally oxidized to form SiO.sub.2 films 2 and 3 thereon. As shown in FIG. 1B, the SiO.sub.2 film 3 on the lower surface of the silicon substrate 1 is then removed by an etching solution such as an HF-based solution. In this case, the SiO.sub.2 film 2 is covered in advance with a photoresist (not shown) so that the film 2 is prevented from being etched.
After the photoresist is removed from the SiO.sub.2 film 2, the resultant structure is heated to a high temperature of 1,000.degree. C. or more in an O.sub.2 atmosphere by using POCl.sub.3 as a source of impurity diffusion, thereby performing impurity diffusion. As a result, a phosphorus diffused layer 4 is formed on the lower surface of the p-type silicon substrate 1, as shown in FIG. lC. At the same time, P.sub.2 O.sub.5 -based PSG (phosphorus-silica-glass) films 5 and 6 are formed on the phosphorus diffused layer 4 and the SiO.sub.2 film 2 on the upper surface of the substrate, respectively.
As shown in FIG. 1D, an SiO.sub.2 film 7 is deposited by a CVD method on the PSG film 5 formed on the lower surface side. Thereafter, as shown in FIG. 1E, a photoresist 8 is applied to the SiO.sub.2 film 7.
After a photoresist (not shown) is applied to the PSG film 6 on the upper surface side, the photoresist film is patterned in a predetermined shape. Using this photoresist pattern as a mask, the PSG film 6 and the SiO.sub.2 film 2 are etched using an HF-based etching solution to define an element formation region and an element isolation region. During etching, the SiO.sub.2 film 7 and the PSG film 5 are prevented from being etched owing to the presence of the photoresist 8. A predetermined manufacturing process such as a bipolar IC manufacturing process is then performed to prepare a semiconductor device.
In the step of FIG. 1D, if after the formation of the SiO.sub.2 film 7 an Si.sub.3 N.sub.4 film having an etching resistant property against the HF-based etching solution is formed thereon, it becomes unnecessary to form the photoresist 8 in FIG. 1E.
According to the conventional manufacturing process described above, the gettering can effectively be performed owing to the presence of the phosphorus diffused layer 4 formed on the lower surface of the p-type silicon substrate 1. At the same time, the SiO.sub.2 film 7 can prevent an out diffusion of phosphorus from the phosphorus diffused layer 4 and the PSG film 5 in a heat-treatment at a high temperature in the steps following the step of FIG. 1E. According to the manufacturing process described above, however, the steps in FIGS. 1A to 1E are required only for the gettering. Accordingly, such a process has a drawback that the number of steps required for manufacturing the semiconductor device is increased, thereby making the manufacturing process undesirably complex.
A process for manufacturing a bipolar IC, as shown in FIGS. 2A and 2B, is known as a process for manufacturing the semiconductor device, which eliminates the above drawback. According to this process, as shown in FIG. 2A, an n.sup.+ -type buried layer 11 is formed in, e.g., a p-type silicon substrate 1, and an n-type silicon epitaxial growth layer 12 is formed on the p-type silicon substrate 1. Thereafter, p.sup.+ -type isolation diffused regions 13 and 14, and a p-type base region 15 are formed. An SiO.sub.2 film 16 is then formed on the surface of the silicon epitaxial growth layer 12. The predetermined portions of the SiO.sub.2 film 16 are etched to form openings 1

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