Active solid-state devices (e.g. – transistors – solid-state diode – Physical configuration of semiconductor – With peripheral feature due to separation of smaller...
Reissue Patent
2007-05-01
2007-05-01
Prenty, Mark V. (Department: 2822)
Active solid-state devices (e.g., transistors, solid-state diode
Physical configuration of semiconductor
With peripheral feature due to separation of smaller...
C257S737000, C257S738000, C257S786000
Reissue Patent
active
10645782
ABSTRACT:
A process for manufacturing a semiconductor device includes defining chip sections on a wafer by scribe lines with each chip section having chip electrodes formed thereon. The wafer is covered with a passivating film except for on the chip electrodes. Aluminum interconnection layers are provided such that each layer is connected to the chip electrode at one end thereof and the other end of the layer is extended towards the central portion of the chip section. A cover coating film is applied on the passivating film and the layers. A number of apertures are formed in the coating film passing therethrough, and bump electrodes are formed at the position corresponding to the apertures. The chip sections are then separated from each other along the scribe lines into semiconductor devices.
REFERENCES:
patent: 3719981 (1973-03-01), Steitz
patent: 3760238 (1973-09-01), Hamer et al.
patent: 4604644 (1986-08-01), Beckham et al.
patent: 4878098 (1989-10-01), Saito et al.
patent: 4907062 (1990-03-01), Fukushima
patent: 4948754 (1990-08-01), Kondo et al.
patent: 5027188 (1991-06-01), Owada et al.
patent: 5049980 (1991-09-01), Saito et al.
patent: 5111278 (1992-05-01), Eichelberger
patent: 5137845 (1992-08-01), Lochon et al.
patent: 5250843 (1993-10-01), Eichelberger
patent: 5289038 (1994-02-01), Amano
patent: 5327013 (1994-07-01), Moore et al.
patent: 5434452 (1995-07-01), Higgins, III
patent: 5554940 (1996-09-01), Hubacher
patent: 5604379 (1997-02-01), Mori
patent: 5844304 (1998-12-01), Kata et al.
patent: 0485760 (1992-05-01), None
patent: 4952973 (1974-05-01), None
patent: 52-087983 (1977-07-01), None
patent: 63-86458 (1988-04-01), None
patent: 63-293965 (1988-11-01), None
patent: 64-57643 (1989-04-01), None
patent: 1-173733 (1989-07-01), None
patent: 1-196856 (1989-08-01), None
patent: 4-373131 (1992-12-01), None
patent: 05-121413 (1993-05-01), None
patent: 5129366 (1993-05-01), None
patent: 5-166812 (1993-07-01), None
patent: 5-218042 (1993-08-01), None
patent: 5-267302 (1993-10-01), None
patent: 677293 (1994-03-01), None
patent: 6-112211 (1994-04-01), None
R. Chanchani et al., “A New mini Ball Grid Array (mBGA) Multichip Module Technology”; International Journal of Microcircuits & Electronic Packaging, 18(1995) Third Quarter, No. 3, Reston, VA, pp. 185-192., Dec. 1995.
Ray-Long Day et al., “A Silicon-on-Silicon Multichip Module Technology with Integrated Bipolar Components in the Substrate”, IEEE Multi-Chip Module Conference MCMC-94, Mar. 15-17, 1994, pp. 64-67.
Chikaki Shinichi
Kata Keiichiro
Foley & Lardner LLP
Prenty Mark V.
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