Semiconductor device manufacturing: process – Including control responsive to sensed condition – Electrical characteristic sensed
Reexamination Certificate
2001-01-12
2003-01-28
Niebling, John F. (Department: 2812)
Semiconductor device manufacturing: process
Including control responsive to sensed condition
Electrical characteristic sensed
Reexamination Certificate
active
06511857
ABSTRACT:
TECHNICAL FIELD
The present invention relates to a method of manufacturing a semiconductor apparatus, and more particularly, to a method of manufacturing a semiconductor apparatus which intends to improve a yield of the semiconductor apparatus by improving a test process.
A conventional semiconductor apparatus has been manufactured in accordance with the following processes.
Device forming process for forming a multiplicity of devices on a wafer.
Probing test process for applying a probing test (a continuity test) to a multiplicity of devices formed on the wafer (a subject to be tested)
Dicing process for dicing the wafer (cutting the wafer at every integrated circuits) after the probing test process is finished so as to form a plurality of chips.
Package process for packaging each of the chips as a semiconductor apparatus
Burn-in test process for applying a burn-in test (a thermal load test) to the semiconductor apparatus (a subject to be tested).
In this case, among the processes mentioned above, the subject to be tested in the probing test and the burn-in test, an external test system and a connecting method are basically the same. That is, there is employed a method of mechanically contacting each of conductive fine probes with each of electrode pads patterned on the subject to be test at a pitch of about some tens to a hundred and some tens &mgr;m, having a length and a width of some tens to a hundred and some tens &mgr;m and a thickness of about 1 &mgr;m and made of an aluminum alloy or the other alloys. As the fine probe, for example, there is employed a narrow probe made of a tungsten (W) or a nickel (Ni) and having a diameter of a tip of some tens &mgr;m and a length of some tens mm.
DISCLOSURE OF THE INVENTION
However, in the probe structure in accordance with the prior art mentioned above, a large area is required for accurately positioning each of the probes so as to fix. Accordingly, it is hard to arrange more probes within the surface, so that a number of the electrode pads and a number of the chips which can be tested at one time have been limited.
Then, techniques for solving the problems mentioned above are disclosed, for example, in Japanese Patent Unexamined Publication No. 1-147374, Japanese Patent Unexamined Publication No. 9-148389, Japanese Patent Unexamined Publication No. 9-243663 and the like.
In Japanese Patent Unexamined Publication No. 1-147374, the structure is made such that a plurality of beam structures are formed on a single Si single crystal flat plate in a direction of a main plane, a projection is formed in each of tips thereof, and a conductor layer is formed in a direction of a fixed end of the beam structure from the projection.
In Japanese Patent Unexamined Publication No. 9-148389, the structure is made such that Si substrate having three layers formed in different shapes are laminated, a piezoelectric component is arranged on the lowermost layer near a plurality of beam structures and the fixed end of each of the beam structures, and conducting means for conducting the tip of the beam structure with an open surface on the uppermost layer is provided.
In Japanese Patent Unexamined Publication No. 9-243663, an elastomer is interposed between a Si substrate having an aggregate of projections conducting with an external portion and a fixed plate.
However, in Japanese Patent Unexamined Publication No. 1-147374, since a terminal end (an electrode) of a wire within the Si substrate is always formed on substantially the same surface as a probe (projection) forming surface within the Si substrate, there is a problem that the subject to be tested is interfered when performing an electric connection forward from the electrode.
Further, in Japanese Patent Unexamined Publication No. 9-148389, since it is necessary to provide the piezoelectric component in the middle of the beam structure, there is a great problem in view of a cost and a yield in the case of forming a multiplicity of probes.
Still further, in Japanese Patent Unexamined Publication No. 9-243663, the elastomer is directly provided on the back surface of the Si substrate in the structure of the test structure, however, a through groove is always formed in the periphery of each of the beams in the case that the beam structure is provided, so that there is a possibility that it flows out to a side of the subject to be tested due to a pressure at a time of pressing. Further, there is a possibility that the Si substrate weakened by an etching due to a lot of load necessary at a time of testing the subject to be tested in a lump is broken.
An object of the present invention is to make it possible to test an electrode pad of a wafer in a large area and in a lump, in an electric characteristic testing process corresponding to a process of semiconductor apparatus manufacturing processes.
In order to achieve the object mentioned above, in accordance with the present invention, there is provided a method of manufacturing a semiconductor apparatus comprising:
a device forming process for forming a multiplicity of devices on a wafer;
a probing test process for applying a probing test to the wafer (a subject to be tested) on which the multiplicity of devices are formed; and
a burn-in test process for applying a burn-in test to the wafer
8
(a subject to be tested) on which the multiplicity of devices are formed, or chip thereof
wherein the structure is made as follows.
(1) In the probing test process and/or the burn-in test process, a conductive projection is provided on a main surface, and there is included a process for pressing the projection of a test structure in which the projection and a pad provided on a surface opposite to the main surface are electrically connected to a desired position of the subject to be tested.
(2) In the item (1), the test structure is provided with a conductive projection on a main surface, and there are provided a first plate member in which the projection and the pad provided on the surface opposite to the main surface are electrically connected, a second plate member arranged on the side of a surface forming the pad of the first plate member and in which the pad and a wire formed on the second plate member are electrically connected, and a third plate member arranged between the first plate member and the second plate member, formed by a material having a Young's modulus of 60 GPa or more and having a thickness of 100 &mgr;m or more.
(3) In the item (2), a number of test conductor portions existing within a projection surface of the first plate member to the wafer or chip in a state of pressing said projections to a desired position of said wafer or chip and a number of the projections formed in the first plate member formed in an electrically independent manner are equal to each other.
(4) In the item (2) or (3), a plurality of the projections are present and a through groove crossing over a straight line connecting adjacent two projections is provided in the first plate member.
(5) In any one of the items (2) to (4), a space is present between the projection and the third plate member.
(6) In any one of the items (1) to (5), a plurality of the first plate members are provided within a substantially the same plane.
(7) In any one of the items (1) to (6), a part other than the projection of the first plate member or all the area and the subject to be tested are in contact when pressing the projection at a desired position of the subject to be tested.
The inventors of the present application have searched a known art on the basis of the result of the present invention. As a result, Japanese Patent Unexamined Publication No. 5-243344, Japanese Patent Unexamined Publication No. 6-123746, Japanese Patent Unexamined Publication No. 7-7052 and Japanese Patent Unexamined Publication No. 8-148553 are listed up. However, none of them describes the present invention as mentioned below.
In Japanese Patent Unexamined Publication No. 5-243344, there is disclosed a structure in which a plurality of metal projections are formed on a thin and flexible thin film, that is,
Akashi Teruhisa
Ariga Akihiko
Ban Naoto
Endo Yoshishige
Harada Takeshi
Hitachi , Ltd.
Niebling John F.
Stevenson André C.
LandOfFree
Process for manufacturing semiconductor device does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Process for manufacturing semiconductor device, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Process for manufacturing semiconductor device will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3048852