Process for manufacturing semiconductor device

Details Process for manufacturing semiconductor device Process for manufacturing semiconductor device

1998-12-21

2003-05-13

Chaudhuri, Olik (Department: 2823)

Semiconductor device manufacturing: process

Gettering of substrate

C438S438000, C438S583000

Reexamination Certificate

active

06562699

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to a process for fabricating a semiconductor device. In particular, it relates to a process for fabricating a semiconductor device wherein contaminants existing on a surface of a silicon layer and in an subsurface thereof are removed effectively before the formation of an electrode on the silicon layer, whereby the electrode having a low resistance, high heat resistance and uniform thickness can be formed.
RELATED ART
A gate electrode of an N-type field-effect transistor is conventionally formed by the below-described process using a salicide technique.
First, as shown in FIG.
7
(
a
), a polysilicon film is deposited on a silicon substrate
301
on which a p-well region
302
, a field oxide film
303
and a gate oxide film
304
have been formed, and the polysilicon film is patterned by a reactive ion etching (RIE) method with an etching gas containing a halogen using an etching mask
306
to form a gate electrode
305
.
Then, as shown in FIG.
7
(
b
), impurity ions are implanted to be contained in a low concentration in the resulting silicon substrate
301
with intervention of a protective film
307
of silicon oxide against ion implantation to form an LDD (Lightly Doped Drain) region
308
.
Subsequently, as shown in FIG.
7
(
c
), a silicon oxide film
309
is deposited on the entire surface of the resulting silicon substrate
301
and as shown in FIG.
7
(
d
), the silicon oxide film
309
is etched back by the RIE method to form a sidewall spacer
310
.
Next, as shown in FIG.
7
(
e
), an ion implantation is performed again via a protective film
312
against ion implantation, followed by thermal treatment, to form a source/drain region
313
.
Then, as shown in FIG.
7
(
f
), the protective film
312
against ion implantation is removed, and then a titanium film
314
is deposited, followed by thermal treatment by an RTA (Rapid Thermal Annealing) method under nitrogen atmosphere to react the titanium film
314
with silicon
301
and
305
to form a titanium silicide film
315
.
Thereafter, as shown in FIG.
7
(
g
), an unreacted titanium film and a titanium nitride film formed on the surface are selectively removed using a mixture solution of sulfuric acid and aqueous hydrogen peroxide to form titanium silicide electrodes on the source/drain region
308
and the gate electrode
305
in self-alignment.
In such a conventional process for forming an electrode as described above, there are problems in that a spontaneous oxide film may form on the silicon substrate after etching, ion implantation, thermal treatment or the like and in that the layers may be damaged by etching.
Further, in the process shown in FIG.
7
(
d
), for example, since the uniformity in thickness, the etching rate and the like of the oxide film
309
may vary, the oxide film
309
is over-etched by about 10 to 30% of the thickness thereof. Therefore, it is also a problem that the surface of the silicon substrate is directly exposed to a halogen-containing etching gas, for example, such as CHF
3
, CF
4
or the like, and thereby that the surface of the silicon substrate is contaminated by halogen atoms in the etching gas.
Under these circumstances, for example, Japanese Unexamined Patent Publication No. Hei 8-115890 proposes a method for removing the spontaneous oxide film by depositing a metal layer, subjecting to thermal treatment to form a silicide layer and removing the silicide layer. Further, Japanese Unexamined Patent Publications Nos. Sho 62-94937 and Hei 8-250463 propose methods for removing the damaged-by-etching layer by forming an oxide film using a sputtering method or by sacrificial oxidation and removing the oxide film.
Further, against the contamination of the surface of the substrate, utilized is an ashing treatment or a washing treatment of the surface of the substrate with an acid or alkaline solution such as a mixture solution of sulfuric acid and aqueous hydrogen peroxide, a mixture solution of hydrochloric acid and aqueous hydrogen peroxide, a mixture solution of ammonia and aqueous hydrogen peroxide or the like.
However, in these methods, since the surface layer on the silicon substrate is removed or sputtered, such problems are still unsolved that the damage of the surface of the substrate cannot completely be removed and the contaminants cannot be sufficiently removed.
Therefore, when the electrode formed by the above-described method is used for fabricating a semiconductor device, there is a problem in that characteristics of the resulting semiconductor device are not satisfactory.
DISCLOSURE OF THE INVENTION
The present invention provides a process for fabricating a semiconductor device comprising removing halogen atoms existing on a surface of a silicon layer and in a subsurface thereof so that the concentration thereof is reduced to 100 ppm or lower, and forming an electrode on the resulting silicon layer.
Further, the present invention provides a process for fabricating a semiconductor device comprising forming a gate oxide film and a gate electrode on a silicon substrate, depositing an insulating film on the resulting silicon substrate which includes the gate electrode, forming a sidewall spacer on a side wall of the gate electrode by etching back the insulating film using a halogen-containing etching gas, forming a titanium film on the resulting silicon substrate at a temperature of the substrate not higher than 500° C., removing the titanium film, and depositing a refractory metal on the resulting silicon substrate, followed by thermal treatment, to form a refractory metal silicide film in a region where the silicon substrate is in direct contact with the refractory metal.


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patent: 4981550 (1991-01-01), Huttemann et al.
patent: 5726096 (1998-03-01), Jung
patent: 5830802 (1998-11-01), Tseng et al.
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patent: 6207562 (2001-03-01), Han
patent: 61258434 (1986-11-01), None
patent: 62094937 (1987-05-01), None
patent: 8115890 (1996-05-01), None
patent: 8115890 (1996-07-01), None
patent: 8250463 (1996-09-01), None
patent: WO 97/05298 (1997-02-01), None
W.D. Su, Double Spacer Technique for Ti Self-aligned Silicidation Technology, (IEEE), pp. 113-116, 1991.*
Kotaki et al., Novel Ultra-Clean Self Aligned Silicide (Salicide) Technology Using Double Titanium Deposited Silicide (DTD) Process for 0.1 mm Gate Electrode, Japan J. Applied Physics, vol. 37 pp. 1174-1178 (1998).*
Kotaki et al., “Novel Contamination Restrained Silicidation Processing . . . ” Technical Digest of the International Electron Devices Meting, XP000624754, pp. 457-460, Dec. 10, 1995.

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