Semiconductor device manufacturing: process – Formation of electrically isolated lateral semiconductive... – Grooved and refilled with deposited dielectric material
Reexamination Certificate
2000-06-06
2002-02-12
Smith, Matthew (Department: 2825)
Semiconductor device manufacturing: process
Formation of electrically isolated lateral semiconductive...
Grooved and refilled with deposited dielectric material
C438S427000, C438S438000, C438S617000, C438S719000, C438S724000
Reexamination Certificate
active
06346457
ABSTRACT:
CROSS-REFERENCE TO RELATED APPLICATION
This application is related to Japanese application No. HEI 11(1999)-273911 filed on Sep. 28, 1999, whose priority is claimed under 35 USC § 119, the disclosure of which is incorporated by reference in its entirety.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a process for manufacturing a semiconductor device. More particularly, it relates to a process for device isolation utilizing shallow trench isolation (hereinafter referred to as STI) method.
2. Description of Related Art
Conventionally, LOCOS (Local Oxidization of Silicon) method has been widely used as a method for forming a device isolation region in a semiconductor device. As a demand for miniaturization of devices rises, LOCOS method by thermal oxidization has suffered from the generation of bird's beaks.
Then, STI method has been proposed to solve such a drawback of LOCOS method. STI method comprises the following steps. First, a groove, ex. a trench, is formed in a silicon substrate and an insulating film is formed to fill the trench. Then the insulating film formed on a region other than the trench is removed by chemical mechanical polishing (CMP) method. Through these steps, a device isolation region is formed. As compared with LOCOS method, STI method forms the insulating film by plasma CVD method or the like, which reduces thermal processes. Therefore, the bird's beaks occurred in LOCOS method can be greatly prevented.
However, STI method also has particular drawbacks. LOCOS method utilizes thermal oxidization as described above, so that after the device isolation region is formed, the surface has a relatively gentle undulation. In STI method, an edge portion of the device isolation region obtained after CMP method of the insulating film projects from the surface of the substrate and the projected portion forms sidewalls almost perpendicular to the substrate. Accordingly, at the formation of gate electrodes in a later step, a resist pattern formed by photolithography may excessively be narrowed or polysilicon (a gate electrode material)
25
may remain as shown in
FIG. 4
after the gate electrodes is formed by etching.
FIG. 4
is a view for illustrating drawbacks of the prior art, in which reference numeral
21
denotes a silicon substrate,
22
a STI region,
23
a gate insulating film and
24
a gate electrode.
In connection to the above drawbacks, for example, Japanese Unexamined Patent Publication No. HEI 10(1998)-144781 discloses a method for preventing the formation of level differences in the STI regions by using a SiN film as a CMP stopper in the formation of the STI regions. Further, a method for removing the projected portion in the STI regions by etching back has also been proposed.
Hereinafter, the above process using the CMP stopper will be explained with reference to FIGS.
5
(
a
) to
5
(
g
). FIGS.
5
(
a
) to
5
(
g
) illustrate a conventional process for forming the STI region.
First, on a silicon substrate
11
, a first silicon nitride film
12
, a first silicon oxide film
13
, a second silicon nitride film
14
and a second silicon oxide film
15
are formed in sequence by CVD method (see FIG.
5
(
a
)). Then, a resist pattern (not shown) having an opening in a region for forming a trench is formed by lithography. Using the resist pattern as a mask, anisotropic etching is performed by RIE method to form a trench
11
A extending from the surface of the second silicon oxide film
15
into the silicon substrate
11
(see FIG.
5
(
b
)).
The resist pattern is removed, and then a buried insulating film (a third silicon oxide film
16
) and a third silicon nitride film
17
are formed by CVD method as shown in FIG.
5
(
c
). The third silicon nitride film
17
inhibits the formation of a concave in the third silicon oxide film
16
during polishing by CMP method in a later step.
As shown in FIG.
5
(
d
), the polishing by CMP method is performed on the third silicon nitride film
17
and continued until the surface of the second silicon nitride film
14
is exposed. Then, as shown in FIG.
5
(
e
), the remaining third silicon nitride film
17
and the second silicon nitride film
14
are removed by wet etching. Then, as shown in FIG.
5
(
f
), the first silicon oxide film
13
is removed and a convex portion
16
A of the third silicon oxide film
16
is reduced in height by RIE method. Thereafter, as shown in FIG.
5
(
g
), the first silicon nitride film
12
is removed by wet etching to expose the surface of the silicon substrate
11
. Thus, the STI region is formed.
This process, however, forms a large number of stopper films (
14
,
13
and
12
) for CMP and etching back processes and requires removal processes for the respective films. Therefore, the number of production steps is multiplied, which increases the production costs.
SUMMARY OF THE INVENTION
According to the present invention, provided is a process for manufacturing a semiconductor device comprising the steps of:
depositing a polish-stopper film on a semiconductor substrate, applying a photoresist on the polish-stopper film and removing the photoresist from a region for forming a device isolation region to form an opening;
dry etching using the photoresist as an etching mask to form a trench of a predetermined depth in the semiconductor substrate;
removing the photoresist;
forming a first insulating film and a second insulating film in sequence to bury the trench, the second insulating film being capable of being etched by the same etching step as that for the first insulating film and having an etching rate greater than that of the first insulating film;
polishing the first and second insulating films by CMP method until a surface of the polish-stopper film is exposed;
removing the polish-stopper film; and
removing the first and second insulating films projected from a surface of the semiconductor substrate by etching using the same etchant, thereby to form a device isolation region in the trench.
These and other objects of the present application will become more readily apparent from the detailed description given hereinafter. However, it should be understood that the detailed description and specific examples, while indicating preferred embodiments of the invention, are given by way of illustration only, since various changes and modifications within the spirit and scope of the invention will become apparent to those skilled in the art from this detailed description.
REFERENCES:
patent: 6048775 (2000-04-01), Yao et al.
patent: 6140242 (2000-10-01), Oh et al.
patent: 10-144781 (1998-05-01), None
Anya Igwe U.
Nixon & Vanderhye P.C.
Sharp Kabushiki Kaisha
Smith Matthew
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