Metal working – Method of mechanical manufacture – Electrical device making
Reexamination Certificate
2000-07-19
2003-12-16
Chang, Richard (Department: 3729)
Metal working
Method of mechanical manufacture
Electrical device making
C029S830000, C029S846000, C029S847000, C427S097100, C427S099300, C430S311000, C430S313000, C430S315000, C174S262000, C174S257000, C205S125000
Reexamination Certificate
active
06662442
ABSTRACT:
FIELD OF THE INVENTION
This invention relates to a process for producing a printed wiring board and, more particularly, a printed wiring board suitable as an interposer of chip size packages for electrically connecting a semiconductor chip to an external printed wiring board and a process for producing the same.
BACKGROUND OF THE INVENTION
With the recent tendencies for electronic equipment to have smaller size and weight, semiconductor chip packages for mounting have been reduced in dimensions. In this line, so-called chip size packages (also called chip scale packages) have been developed as means for providing minimally packaged chips which are about the size of bare chips.
As shown in
FIG. 9
, a chip size package has an interposer
3
, which is interposed between a semiconductor chip
1
and an external printed wiring board
2
to establish an electrical connection between the electrodes (not shown) of the chip
1
and those of the external printed wiring board
2
.
The interposer
3
has a three-layer structure composed of an outer insulator layer
4
, a conductor layer
6
formed on the outer insulator layer
4
in a prescribed circuit pattern, and an inner insulator layer
7
formed thereon. The outer insulator layer
4
has via-holes
8
mated with the electrodes of the external circuit board
2
. The via-holes
8
provide conducting passages
9
, which connect with outer electrodes
10
of bump form. The inner insulator layer
7
have inner via-holes
11
mated with the electrodes of the chip
1
, on which flat inner electrodes
12
are provided.
The inner insulator layer
7
of the interposer
3
is joined to the back face of the chip
1
to connect the inner electrodes
12
and the electrodes of the chip
1
. In surface mounting, the outer electrodes
10
of the package are connected to the electrodes of the external circuit board
2
, whereby the electrodes of the chip
1
and those of the external printed wiring board
2
are electrically connected via the inner electrodes
12
, the conductor layer
6
, the conducting passages
9
, and the outer electrodes
10
of the interposer
3
. The semiconductor chip
1
has been sealed with a sealant
13
.
In producing such an interposer
3
, it is considered that the conductor layer
6
and the conducting passages
9
can be formed easily by plating techniques. Electroplating, for instance, is illustrated in
FIGS. 11A-11E
. As shown in
FIG. 11A
, an outer insulator layer
4
is formed on a negative electrode
14
for electroplating, and outer via-holes
8
are made through the outer insulator layer
4
. A thin metal film
15
is formed on the upper surface of the outer insulator layer
4
and the upright wall and the bottom of the outer via-holes
8
as shown in
FIG. 11B
by, for example, sputtering. A plating resist
16
is formed on the thin metal film
15
at positions corresponding to the gaps between wires of a prescribed circuit pattern as shown in FIG.
11
C. As shown in
FIG. 11D
, metal is deposited in the outer via-holes
8
to form conducting passages
9
and then on the conducting passages
9
and on the outer insulator layer
4
to form a conductor layer
6
of prescribed circuit pattern by electroplating. Then, the plating resist
16
and the part of the thin metal film
15
where the plating resist
16
has existed are removed by etching to leave the conductor layer
6
and the conducting passages
9
as shown in FIG.
11
E.
Where plating is carried out in the above-described method, it is conceivable that the following problem occurs. Because metal deposited on the bottom of the outer via-hole
8
and metal deposited on the upper surface of the outer insulator layer
4
grows in almost the same manner, the part formed of the metal deposited on the bottom of the outer via-hole
8
(i.e., the conducting passage
9
and the part of the conductor layer
6
formed on the conducting passage
9
) will have sunk in to make a shallow dent by the end of the plating, compared with the level of the other part formed of the metal deposited on the upper surface of the outer insulator layer
4
(i.e., the part of the conductor layer
6
that is not in contact with the conducting passage
9
).
Should there be such a dent on the conductor layer
6
, the inner insulator layer
7
formed thereon will also have a corresponding dent to have an uneven surface as illustrated in FIG.
10
. This unevenness reduces adhesion between the semiconductor chip
1
and the inner insulator layer
7
, or air trapped in the gap
17
between the chip
1
and the dent may expand thermally to cause separation (blistering), causing reduction in reliability.
SUMMARY OF THE INVENTION
An object of the present invention is to provide a process for producing a printed wiring board, in which a conductor layer can be formed without unevenness and has good adhesion to an insulator layer formed thereon to secure reliability.
Another object of the present invention is to provide a reliable printed wiring board produced by the process.
The invention provides a process for producing a printed wiring board comprising the steps of (1) forming a first insulator layer having first through-holes on a substrate, (2) forming conducting passages through the first through-holes by plating with metal up to substantially the same level as the upper surface of the first insulator layer, (3) forming a thin metal film on the first insulator layer and on the conducting passages, (4) forming a conductor layer in a prescribed circuit pattern on the thin metal film by plating, (5) removing the part of the thin metal film on which the conductor layer is not formed, (6) forming a second insulator layer on the conductor layer, and (7) removing the substrate.
In a preferred embodiment, the substrate is made of a material capable of serving as a negative electrode in electroplating. In another preferred embodiment, the second insulator layer has adhesiveness. In still another preferred embodiment, the circuit pattern of the conductor layer formed on the thin metal film by plating has an interval of 30 &mgr;m or smaller among the wires.
The invention also provides a printed wiring board produced by the above process. The printed wiring board is suitable as an interposer for chip size packages.
According to the invention, since the second insulator layer, which is to be joined to the back face of a semiconductor chip, is formed on the conductor layer which is substantially free from unevenness, it is adhered to a semiconductor chip with no gaps, and the reliability of the semiconductor device can be improved. Where the insulator layer has adhesiveness, the printed wiring board can be adhered to a semiconductor chip with good adhesion simply by uniform pressure application to secure reliability. Where the circuit pattern has an interval of 30 &mgr;m or smaller, the possibility of the second insulator layer's being sank in the gap of the circuit pattern can be lessened. The flatness of the surface of the second insulator layer is thus enhanced, securing the good adhesion to a semiconductor chip, which leads to improved reliability of the semiconductor device.
REFERENCES:
patent: 5246817 (1993-09-01), Shipley, Jr.
patent: 5323520 (1994-06-01), Peters et al.
patent: 6162580 (2000-12-01), Matsuoka et al.
patent: 6255039 (2001-07-01), Xu et al.
patent: A-7-186323 (1995-07-01), None
patent: A-10-135598 (1998-05-01), None
Fujii Hirofumi
Matsui Kouji
Mune Kazunori
Tanigawa Satoshi
Chang Richard
Nitto Denko Corporation
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