Process for manufacturing metal-semiconductor field-effect trans

Details Process for manufacturing metal-semiconductor field-effect trans Process for manufacturing metal-semiconductor field-effect trans

1986-08-25

1988-03-15

Hearn, Brian E.

Fishing, trapping, and vermin destroying

357 49, 357 65, 357 41, 156653, 156657, 1566591, 156668, 1566611, 437 41, 437187, 437924, 437944, 430315, 430317, B44C 122

Patent

active

047313390

ABSTRACT:
A single-level photoresist process is used to make metal-semiconductor field-effect transistors (MESFETs) having more uniform threshold voltages. An N.sup.- layer is formed in a semi-insulating semiconductor, followed by formation of a dummy gate using a single-level photoresist process. Using the dummy gate as a mask, ions are implanted to form an N.sup.+ region. The length of the dummy gate is then reduced by plasma etching. A dielectric is deposited over the N.sup.+ region, the N.sup.+ /N.sup.- interface, and the exposed portion of the N.sup.- layer. The dummy gate is lifted off to define a self-aligned, submicron gate opening. The gate opening on the N.sup.- layer is reactive ion etched to obtain the desired threshold voltage, and covered with a Schottky gate metal deposit.

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P. C. Chao, "0.2 Micron Length T-Shaped Gate Fabrication Using Angle Evaporation", IEEE Electron Device Letters, vol. EDL-4, No. 4, Apr. 1983.
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Kato et al., "Influence of n.sup.+ -Layer-Gate Gap on Short-Channel Effects of GaAs Self-Aligned MESFET's (SAINT), IEEE Electron Device Letters, vol. EDL-4, No. 11, 11-85.
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