Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Charge transfer device
Patent
1993-03-12
1995-10-10
Limanek, Robert P.
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Charge transfer device
437186, 437 50, 437 53, H01L 3118, H01L 2182
Patent
active
054573327
DESCRIPTION:
BRIEF SUMMARY
BACKGROUND OF THE INVENTION
The invention relates to integrated circuits.
In certain applications, and mention will be made by way of example of charge-coupled devices, there is a need to produce electrodes side by side which are very close to each other but which do not overlap too much in order not to create too high a parasitic capacitance between the two electrodes and, in the case of photosensitive devices, in order for the photosensitivity not to be reduced by this overlap.
For example, in a charge-coupled register, electrodes are juxtaposed so that a packet of charges stored in a semiconductor substrate beneath one electrode can be transferred beneath an adjacent electrode by simply applying suitable potentials to the electrodes. If the electrodes are not sufficiently close to each other the transfer runs the risk of being incomplete. However, in order to produce electrodes very close together, existing techniques require in practice a partial overlap (with intermediate insulation) of one electrode by the other to be provided.
SUMMARY OF THE INVENTION
The invention provides a novel manufacturing process intended to improve the production of integrated circuits having to have electrodes juxtaposed very close together.
According to the invention, it is essentially provided to deposit a first silicon layer onto a substrate, to deposit on top of this layer an oxidation-preventing masking layer (preferably made from silicon nitride or a conventional combination of silicon oxide and silicon nitride), to photoetch the masking layer in order to open up the latter over a small width, to oxidise, over its entire thickness, the first silicon layer at that place where it is not masked, to remove the silicon oxide formed during this oxidation, which forms an upwardly-open hollowed-out space delimited by the first silicon layer at that place where it has not been oxidised and by the oxidation-preventing masking layer, to form a thin insulating layer on the side walls of the first layer along the edges of the hollowed-out space, to deposit a second silicon layer totally filling this space, the ratio between the width of the hollowed-out space and the thickness of the second silicon layer being chosen to be sufficiently small for the silicon thickness of the second layer inside the hollowed-out space to be higher than outside and, finally, to remove the totality of the thickness of the second layer from outside the hollowed-out space while allowing silicon to remain in this space.
The approximate maximum value of the ratio between the width of the hollowed-out space and the thickness of the second silicon layer is roughly 2 to 4. It should be noted that this value is given above all by way of indication, the important point being the final result, that is to say the possibility of forming an overthickness in the hollowed-out space such that, even after etching of the totality of the thickness of the second silicon layer, a complete silicon layer coming into contact with the insulated side walls of the first layer remains in the opening. By way of example, with current low-pressure vapour-phase processes for depositing polycrystalline silicon, it is possible to have a width of the hollowed-out space up to roughly 1.5 micrometers wide for a thickness of roughly 1 micrometer of the second silicon layer.
Most of the time the invention will be used for electrodes deposited on top of a thin insulating layer; as a consequence, in this case, it is necessary to consider that the substrate is a semiconductor substrate covered with a thin insulating layer (silicon oxide and/or silicon nitride a few hundreds of angstroms thick); the first silicon layer is deposited onto this thin insulating layer; and if the second electrode has also to be deposited onto an insulating layer, it is envisaged that, after the step for removing the oxide formed by oxidation of the first silicon layer, a thin insulating layer is reformed on the substrate in the opening left free.
After forming the electrodes in the manner indicated hereinabove,
REFERENCES:
patent: 4251571 (1981-02-01), Garbarino et al.
patent: 4352237 (1982-10-01), Widmann
patent: 4742027 (1988-05-01), Blanchard et al.
patent: 5135889 (1992-08-01), Allen
patent: 5219768 (1993-06-01), Okita
patent: 5346838 (1994-09-01), Ueno
IBM TDB, vol. 20, No. 4, Sep. 1977, pp. 1430-1432.
IBM TDB, vol. 20, No. 1, Jun. 1977, p. 131.
List of U.S. patent applications and patents by the Inventor.
Limanek Robert P.
Plottel Roland
Thomson-CSF Semiconducteurs Specifiques
Williams Alexander Oscar
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