Process for manufacturing electronic device packages

Metal working – Electric condenser making – Solid dielectric type

Reexamination Certificate

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Reexamination Certificate

active

06647603

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The invention relates to a process for manufacturing electronic device packages, more particularly to a process for manufacturing electronic device packages that facilitates automation and mass-production and that is cost-effective.
2. Description of the Related Art
A conventional electronic device package, such as a surge suppressor, a Y-type capacitor, a negative temperature coefficient (NTC) thermistor or a positive temperature coefficient (PTC) thermistor, is shown in FIG.
1
. The process for manufacturing the conventional electronic device package comprises the steps of forming two electrode layers
2
on two opposite side faces of an electronic element
1
, soldering upper sections of two connecting legs
3
onto the electrode layers
2
on the side faces of the electronic element
1
, and forming an insulating layer
4
on the electronic element
1
in a manner that the insulating layer
4
encloses the electronic element
1
and the upper sections of the connecting legs
3
so as to produce the electronic device package.
However, the aforementioned manufacturing process suffers from the following drawbacks:
1. Since the connecting legs
3
of the electronic device packages are formed individually, a batch of connecting legs
3
are manually arranged and are adhered onto an adhesive tape (not shown) prior to disposing and soldering of the connecting legs
3
onto the electronic elements
1
. The adhesive tape is removed thereafter. Therefore, the aforementioned process is complicated and laborious and can not be mass-produced with the use of an automatic apparatus.
2. Since the connecting legs
3
are formed as circular metal conductive wires, the contacting areas between the connecting legs
3
and the electronic elements
1
are relatively small, thereby resulting in an insufficient soldering effect. Even though the upper sections of the connecting legs
3
could be pressed into a flat form, an additional step is required and the contacting areas between the connecting legs
3
and the electronic elements
1
are still insufficient for effective soldering.
SUMMARY OF THE INVENTION
Therefore, the object of the present invention is to provide a process for manufacturing electronic device packages with stable qualities and superior soldering effects.
According to the present invention, a process for manufacturing electronic device packages comprises the steps of:
preparing a plurality of electronic elements, each of which has two opposite side faces and each of which is formed with two electrode layers on the side faces, respectively;
preparing a metal sheet extending in a longitudinal direction;
forming the metal sheet into a runner part that extends in the longitudinal direction, and a plurality of spaced apart terminal parts that are connected to the runner part and that are aligned in the longitudinal direction, each of the terminal parts including a pair of spaced apart connecting legs that have lower inserting sections connected to the runner part, and upper soldering sections which extend from the lower inserting sections and which are offset from each other in a transverse direction relative to the longitudinal direction so as to define an inserting gap therebetween;
positioning each of the electronic elements into the inserting gap in a respective one of the terminal parts in a manner that the upper soldering sections of the connecting legs of the respective one of the terminal parts confront the electrode layers on the side faces of the electronic element, respectively; and
respectively connecting the side faces of each of the electronic elements to the upper soldering sections of the connecting legs of the respective one of the terminal parts via soldering.


REFERENCES:
patent: 4497012 (1985-01-01), Gottlieb et al.
patent: 4631824 (1986-12-01), King
patent: 4639988 (1987-02-01), Goto et al.
patent: 4785533 (1988-11-01), Seino et al.
patent: 4989318 (1991-02-01), Utunomiya et al.
patent: 5060117 (1991-10-01), Dorlane et al.
patent: 5307929 (1994-05-01), Seidler
patent: 5867895 (1999-02-01), Beneden et al.

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