Process for manufacturing CMOS integrated devices with reduced g

Details Process for manufacturing CMOS integrated devices with reduced g Process for manufacturing CMOS integrated devices with reduced g

1988-12-14

1990-11-06

Hearn, Brian E.

Fishing, trapping, and vermin destroying

437 58, 437 44, 437 45, 437150, 357 238, H01L 21336

Patent

active

049686399

ABSTRACT:
A process for manufacturing CMOS integrated devices with gate lengths of less than one micron and high supply voltage is described. In order to improve the resistance of CMOS devices to breakdown and punch-through phenomena without cost increases with respect to conventional CMOS processes and limiting as much as possible the introduction of resistances in series to the transistors, less doped source and drain regions being provided in only one of the two MOS transistors, e.g. in the N-channel transistor, to increase the breakdown voltage, an oppositely doped region, e.g. with P-type doping, being provided around the source and drain regions of this first transistor to protect this first transistor against punch-through, and doped wells being provided around the source and drain regions of the complementary transistor, which is e.g. a P-channel transistor; the doped wells being oppositely doped with respect to the source and drain regions but having a lower doping level than the region of the body of semiconductor material which accommodates the complementary transistor, in order to increase the breakdown voltage of the P-channel complementary transistor.

REFERENCES:
patent: 4306916 (1981-12-01), Wollesen et al.
patent: 4385947 (1983-05-01), Halfacre et al.
patent: 4420344 (1983-12-01), Davies et al.
patent: 4642878 (1987-02-01), Maeda
patent: 4764477 (1988-08-01), Chang et al.
"Self-Aligned P.sup.+ Implanted Regions . . . ," IBM Technical Disclosure Bulletin, vol. 31, No. 4, Sep. 1988, pp. 421-423.

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