Process for manufacturing an interconnect for testing a semicond

Details Process for manufacturing an interconnect for testing a semicond Process for manufacturing an interconnect for testing a semicond

1995-09-05

1998-02-10

Graybill, David

Semiconductor device manufacturing: process

With measuring or testing

Packaging or treatment of packaged semiconductor

438 17, 438611, 438665, 438666, 438673, 438701, 438734, 438736, 29 2501, H01L 2166, H01L 21603

Patent

active

057162182

ABSTRACT:
A method for forming a compliant interconnect for making a temporary (or permanent) electrical connection with a semiconductor die. The compliant interconnect includes raised contacts having penetrating projections for penetrating contact locations on the die (e.g., bond pads) to a limited penetration depth. In an illustrative embodiment the raised contacts are formed on a silicon substrate as raised pillars with a hollow etched interior portion. A tip of the raised contacts is formed as a thin flexible membrane to permit a desired amount of flexure or compliancy under loading from the die held in a test fixture. In an alternate embodiment the raised contacts are formed on a hollow flexible base portion. In another alternate embodiment the raised contacts are formed on a flexible membrane mounted to a support substrate having etched pockets filled with an elastomeric material.

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