Process for manufacturing a semiconductor wafer having...

Semiconductor device manufacturing: process – Formation of electrically isolated lateral semiconductive... – Grooved and refilled with deposited dielectric material

Reexamination Certificate

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C438S404000, C438S405000, C438S413000, C438S442000

Reexamination Certificate

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07906406

ABSTRACT:
A process for manufacturing a semiconductor wafer including SOI-insulation wells includes forming, in a die region of a semiconductor body, buried cavities and semiconductor structural elements, which traverse the buried cavities and are distributed in the die region. The process moreover includes the step of oxidizing selectively first adjacent semiconductor structural elements, arranged inside a closed region, and preventing oxidation of second semiconductor structural elements outside the closed region, so as to form a die buried dielectric layer selectively inside the closed region.

REFERENCES:
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patent: 6777708 (2004-08-01), Lin et al.
patent: 6933590 (2005-08-01), Yamada et al.
patent: 2004/0058506 (2004-03-01), Fukuzumi
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Application No. EP 06-42-5494, European Search Report, European Patent Office, Jan. 11, 2007, 2 pages.
T. Sato et al., “A New Substrate Engineering for the Formation of Empty Space in Silicon (ESS) Induced by Silicon Surface Migration,” IEDM 1999, pp. 517-520.

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