Process for manufacturing a semiconductor memory device

Details Process for manufacturing a semiconductor memory device Process for manufacturing a semiconductor memory device

1984-04-05

1985-08-20

Roy, Upendra

Metal working

Method of mechanical manufacture

Assembling or joining

29576B, 29577C, 148 15, 148175, 148187, 357 91, 357 236, 357 2312, 357 2313, H01L 21425, H01L 21265

Patent

active

045355304

ABSTRACT:
An n-channel MOS dynamic memory cell includes a semiconductor substrate having a p.sup.+ internal region and a p.sup.- surface region disposed on the surface of the internal region except for an n.sup.+ region serving as a bit line, a capacitor electrode disposed above the surface region, and a transfer gate disposed between the capacitor electrode and the n.sup.+ region above the surface region. The surface region except for the n.sup.+ region and a portion of the internal region disposed below the transfer gate are higher in resistivity than at least one of a portion of the internal region disposed below the capacitor electrode and another portion of the internal region disposed below the n.sup.+ region.

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Brodsky, M., "Hardening RAMs Against Sort Errors", Electronics, Apr. 24, 1980, pp. 117-122.
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David Yaney et al., "Alpha-Particle Tracks in Silicon and Their Effect on Dynamic MOS RAM Reliability", IEEE Transactions on Electron Devices, vol. ED-26, No. 1, Jan. 1979, pp. 45-50.

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