Semiconductor device manufacturing: process – Forming bipolar transistor by formation or alteration of... – On insulating substrate or layer
Reexamination Certificate
2000-05-26
2001-12-18
Dang, Trung (Department: 2823)
Semiconductor device manufacturing: process
Forming bipolar transistor by formation or alteration of...
On insulating substrate or layer
C438S410000, C438S413000, C438S355000, C438S362000, C438S363000, C438S443000
Reexamination Certificate
active
06331470
ABSTRACT:
TECHNICAL FIELD
The present invention refers to a process for manufacturing a semiconductor material wafer comprising power regions dielectrically insulated from circuitry regions.
BACKGROUND OF THE INVENTION
As is known, integration of low voltage devices and power devices on a same silicon wafer requires particular isolation structures. For example, power devices with vertical current flow need the capability of withstanding high voltages and currents and of low voltage control components in a same chip. In this case, it is necessary to form, in the wafer, wells that are dielectrically insulated and that house the control components, whilst in the intermediate regions the silicon extends with continuity between the two faces of the wafer and houses the power devices.
One solution for forming such a structure is proposed in Y. Sugawara “Dielectric Isolation Technologies and Power Integrated Circuits”, pp. 150-157, in B. Murari, F. Bertotti, G. A. Vignola “Smart Power ICs—Technologies and Applications”, Springer, 1995. According to this article, the process starts from a SOI (Silicon-On-Insulator) type substrate comprising a bottom silicon layer and a top silicon layer separated by a silicon dioxide layer. Next, portions of the top silicon layer and of the silicon dioxide layer are etched in the areas where the power devices are to be formed. An epitaxial growth is then carried out, and the surface of the wafer is planarized. The structure that is obtained in this way comprises portions having the bottom layer and the top layer separated by buried oxide regions and portions of silicon continuity, in which the epitaxial layer interfaces directly with the bottom layer. Finally, the portions overlying the buried oxide islands are insulated by trenches filled with dielectric material and undergo standard fabrication steps to form the low voltage circuitry, whilst the vertical current flow power devices are formed in the portions of silicon continuity.
The described process presents some drawbacks. Mainly, direct etching of silicon to remove extensive portions of the top silicon layer creates problems. In fact, a dry etch enables only removal of limited portions of silicon, corresponding to approximately 5-10% of the surface of the wafer, whereas to form power devices it is necessary to remove silicon areas corresponding to 50-70% of the wafer surface. Furthermore, a dry etch may easily cause crystallographic damage to the substrate that cannot be eliminated with subsequent treatments. This is particularly disadvantageous in the manufacture of devices using the so-called “Smart Power” technology, because in this case the quality of the silicon is an essential requisite for achieving high levels of performance of the low voltage components.
A wet etch, on the other hand, enables removal of extensive silicon portions, but entails in any case a non-negligible risk of causing crystallographic damage. In addition, wet etching of silicon is a costly process, in so far as it is at present not exploited to any great extent in the industrial field and involves the use of equipment that is not readily available on the market, as well as careful setting up from the chemical standpoint.
More in general, neither of the solutions is very economic, in that they present a very low yield and are not suited for being employed on a large scale.
SUMMARY OF THE INVENTION
The disclosed embodiments of the present invention provide a process for manufacturing structures of the type specified above that is free from the drawbacks described and, in particular, enables a high yield and is economic.
According to the present invention, a process is therefore provided for manufacturing a semiconductor material wafer, including forming a starting wafer having a bottom layer and a top layer, both of semiconductor material, and a buried layer of dielectric material arranged between the bottom layer and the top layer; removing portions of the top layer and forming cavities extending in depth as far as the buried layer, comprising forming sacrificial regions by oxidizing the top layer and removing the sacrificial regions; removing portions of the buried layer beneath the cavity; filling the cavities with filling regions of semiconductor material; and forming lateral insulation regions between the filling regions and circuitry regions in the top layer.
REFERENCES:
patent: 5087580 (1992-02-01), Eklund
patent: 5904535 (1999-05-01), Lee
patent: 5909626 (1999-06-01), Kobayashi
patent: 5930648 (1999-07-01), Yang
patent: 6214694 (2001-04-01), Leobandung et al.
Sugawara, Y., “Large Electric Power Capability Techniques for DI-PICs,”Dielectric Isolation Technologies and Power Ics,pp. 150-157.
Leonardi Salvatore
Sanfilippo Delfo
Dang Trung
Galanthay Theodore E.
Rupnick Charles J.
Seed IP Law Group PLLC
STMicroelectronics S.r.l.
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