Process for manufacturing a semiconductor arrangement

Details Process for manufacturing a semiconductor arrangement Process for manufacturing a semiconductor arrangement

1986-11-17

1987-12-01

Kellogg, Arthur

Fishing, trapping, and vermin destroying

156646, 156653, 156643, B44C 122, C03C 1500

Patent

active

047102640

ABSTRACT:
In a process for manufacturing a semiconductor arrangement, wherein an uneven surface of the semiconductor arrangement is smoothened, there is produced on the uneven surface an insulating layer of such thickness that the insulating layer produced on the surface exhibits an even surface. The insulating layer is then partially removed again.

REFERENCES:
patent: 4377438 (1983-03-01), Moriya et al.
patent: 4566940 (1986-01-01), Itsumi et al.
patent: 4568632 (1986-02-01), Blum et al.
patent: 4601781 (1986-07-01), Mercier et al.
Solid State Photo Resist Technology/Jun. 71, K. R. Dunham, pp. 41-46, "Solid State Technology."
Multilayer Resist Processes & Alternatives, Semiconductor International, Mar. 84, pp. 83-88, D. W. Johnson.
"Layer Resist Systems for Lithography," Solid State Technology/Aug. 81, pp. 74-80, Hatzakis.

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