Metal working – Method of mechanical manufacture – Electrical device making
Reexamination Certificate
2000-09-14
2004-08-17
Chang, Richard (Department: 3729)
Metal working
Method of mechanical manufacture
Electrical device making
C029S846000, C427S096400, C427S097100
Reexamination Certificate
active
06775907
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to a process for manufacturing microelectronic circuitry for printed wiring boards especially with regard to laminate chip carriers. This semi-additive process allows the fabrication of high density circuitry on printed wiring boards having high-aspect plated through holes in high yield with minimal manufacturing steps.
BACKGROUND OF THE INVENTION
As is well known in the art, miniaturization of computer components is a highly desirable goal and this demand has and will continue to dictate the requirement for continually smaller and smaller microelectronic components on packages such as printed wiring boards and laminate chip carriers. Typically, manufacturers employ three technologies for fabrication of such microelectronic components. These include the many varieties of subtractive, semi-additive, and full additive processes for fabricating fine line circuitry on printed wiring boards. Each of these processes has known difficulties and limitations with regard to producing high quality, high density fine-line circuitry.
The subtractive process requires that a full panel plating of copper be employed followed by imaging and developing of an overcoated resist layer and then etching of the copper in areas where the resist was removed. Major problems associated with this process include the fact that large amounts of copper must be etched away and that it is common for undercutting of the remaining circuitry to occur, especially the well known galvanic etching in areas where noble metals are present in proximity to the copper circuitry. There is also the problem of insufficient resolution using the subtractive process, this significantly limits the ultimate density of the fine line circuitry, for example it is well known that as the line or space dimension approaches the thickness of the layer to be etched, subtractive etching becomes unacceptable. To remedy this situation the etch mask must be made larger than the desired feature to allow for this lateral etching.
To circumvent these problems associated with the subtractive process (viz., large waste streams of etch materials and poor resolution due to lateral etching) the additive process has been employed. However, in the case of the additive process, problems are encountered with the need for an adhesion promoting seed layer that must be applied after the photoresist is imaged. This seed layer covers not only the desired areas to be plated but also covers the top surfaces of the photoresist layer. This could cause copper to be plated in areas not desired to be plated. To circumvent this problem, the topmost portions of the photoresist must be chemically or mechanically cleaned of the seed layer. Mechanical etching of this seed layer is known to cause physical defects in the final product due to minute particles causing conductive junctions between what should have been discrete circuit lines. Another potential defect caused by mechanical cleaning is the stress placed on the microcomponent which potentially can cause delamination. Lastly, the process itself is quite expensive due to the required buildup of copper microcircuitry via electroless plating.
To address the problems associated with both the additive and subtractive processes and to further provide electrical continuity to both sides of the substrate, a “semi-additive” process has been utilized by industry in order to make fine line high density printed wiring boards. One variant of this prior art process employs the following steps:
a) imparting an adhesion promoting process on the surface of the substrate package, typically including applying an adhesion promoting layer of a rubber-like material,
b) applying a thin copper foil to the uppermost surface of the adhesion promoting layer,
c) drilling the foiled substrate to create through holes either for the purpose of connecting microcircuitry on the opposing sides of the substrate or for mounting sites for other microelectronic components,
d) electroless plating a thin copper layer to the through-holes and uppermost surface(s) of the foiled substrate,
e) coating the uppermost surface(s) of the copper-clad substrate with a resist that is then exposed and developed to generate vias to the underlying copper layer,
f) electroplating additional copper into these vias to form the desired microcomponent features,
g) removing the remaining photoresist, and
h) etching the now uncovered, original thin copper layer and underlying copper foil to create the discrete microcomponents features and plated through holes.
The semi-additive process as practiced in the art still suffers from several problems. When either sputtering or copper foil was used as the method of applying the initial thin copper layer, the through holes would be untreated and therefore would still have essentially the insulated surface of the resin or glass substrate. This is especially true for high aspect through holes (i.e., thickness of the resin substrate is greater than 5 times the diameter of the through hole). Therefore, additional manufacturing steps were required for preparing those surfaces for plating. As described above, electroless plating of the through holes has been performed after foil lamination but problems have been encountered with adhesion between the electroless copper film plating and the copper foil. Prior art teaches the need to abrade or buff the copper foil before electroless plating in order to ensure good adhesion in the final package. The minimum thickness of the copper foil that can be applied in the semi-additive process is limited by handling problems during the lamination process and this minimum thickness is larger than would be desired in order to create extremely fine line features.
Furthermore, prior art electroless plated layers were still too thick to allow highly dense microelectronic circuitry to be prepared due to the fact that etching as known in the art is largely isotropic and therefore the etch will progress horizontally virtually to the same extent that it will occur vertically. Therefore, the thicker the layer to be etched, the wider the spacing between the features must be otherwise undercutting will become significant and adhesion problems result. In an IS&T article (1970), Celestre and Heiart described a process that involved electroless copper plating of an insulating support to give a conductive layer thickness of 0.3 mil (300 microinches). A resist is then applied, imaged and the circuit lines plated up to a thickness of 1.5 mil. Then the circuits are overplated with nickel and gold. After stripping away the resist, the electroless copper is etched away to complete the circuit panel. As can be seen in this prior art example, the initial electroless layer is approximately 20% of the thickness of the final thickness of the circuitry. As this electroless layer or foil becomes a significant percentage of the total circuit thickness, the semi-additive process in essence takes on the problematic characteristics of the subtractive process. Etching this amount of unwanted copper is not only wasteful and expensive but the process itself will cause significant undesirable lateral etching of desired circuit features. Lateral etching, therefore,- limits the density of the copper circuitry by increasing both the minimum practical line width and the smallest acceptable space between features. This is true even when, as in the case cited, a metal mask such as gold
ickel is employed to protect features from attack.
Widespread use of the semi-additive process where features are plated directly onto the insulating substrate has been limited by poor adhesion between the substrate and the copper. It is desirable to obtain a printed wiring bandwidth the greatest “peel” strength. Stahl, in U.S. Pat. No. 3,625,758, describes a semi-additive process in which a insulative base substrate material, such as phenolic paper board is brushed or sanded to clean and roughen the surface and treated with suitable activating solutions for the electroless deposition of copper. Stahl reports
Boyko Christina M.
Day Robert J.
Stauffer Kristen A.
Chang Richard
Fraley Lawrence R.
Mark Levy & Associates
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