Process for manufacturing a MOS-technology power device chip and

Details Process for manufacturing a MOS-technology power device chip and Process for manufacturing a MOS-technology power device chip and

1997-02-04

1998-12-22

Graybill, David

Semiconductor device manufacturing: process

Making device array and selectively interconnecting

With electrical circuit layout

438136, 438153, 438154, 438155, 438278, 438279, 438283, 438510, 438586, 438587, 438621, H01L 21265, H01L 4900

Patent

active

058518550

ABSTRACT:
A process for manufacturing a MOS-technology power device chip and package assembly, the MOS-technology power device chip comprises a semiconductor material layer in which a plurality of elementary functional units is integrated, each elementary functional unit contributing a respective fraction to an overall current and including a first doped region of a first conductivity type formed in the semiconductor layer, and a second doped region of a second conductivity type formed inside the first doped region; the package comprises a plurality of pins for the external electrical and mechanical connection; the plurality of elementary functional its is composed of sub-pluralities of elementary functional units, the second doped regions of all the elementary functional units of each sub-plurality being contacted by a same respective metal plate electrically insulated from the metal plates contacting the second doped regions of all the elementary functional units of the other sub-pluralities; each of the metal plates are connected, through a respective bonding wire, to a respective pin of the package.

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