Process for manufacturing a high-quality SOI wafer

Details Process for manufacturing a high-quality SOI wafer Process for manufacturing a high-quality SOI wafer

2006-06-06

2010-12-07

Smith, Bradley K (Department: 2894)

Semiconductor device manufacturing: process

Formation of electrically isolated lateral semiconductive...

Grooved and refilled with deposited dielectric material

C438S400000

Reexamination Certificate

active

07846811

ABSTRACT:
In a process for manufacturing a SOI wafer, the following steps are envisaged: forming, in a monolithic body of semiconductor material having a front face, a buried cavity, which extends at a distance from the front face and delimits, with the front face, a surface region of the monolithic body, the surface region being surrounded by a bulk region and forming a flexible membrane suspended above the buried cavity; forming, through the monolithic body, at least one access passage, which reaches the buried cavity; and filling the buried cavity uniformly with an insulating region. The surface region is continuous and formed by a single portion of semiconductor material, and the buried cavity is contained and completely insulated within the monolithic body; the step of forming at least one access passage is performed after the step of forming a buried cavity.

REFERENCES:
patent: 4888300 (1989-12-01), Burton
patent: 5438015 (1995-08-01), Lur et al.
patent: 6773616 (2004-08-01), Chen et al.
patent: 7235456 (2007-06-01), Sato et al.
patent: 7294536 (2007-11-01), Villa et al.
patent: 7491286 (2009-02-01), Kagan et al.
patent: 2003/0168711 (2003-09-01), Villa et al.
patent: 2003/0209814 (2003-11-01), Farrar et al.
patent: 2005/0037593 (2005-02-01), Delpech et al.
patent: 2005/0227492 (2005-10-01), Hah et al.
patent: 0 223 694 (1987-05-01), None
patent: 0 957 515 (1999-11-01), None
patent: 1 073 112 (2001-01-01), None
patent: 1 324 382 (2003-07-01), None
patent: 1577656 (2005-09-01), None
patent: 57 160142 (1982-10-01), None
patent: WO 02/078061 (2002-10-01), None
K. W. Guarini, et al., “Process integration of self-assembled polymer templates into silicon nanofabrication”, J. Vac. Sci. Technol. B 20(6), Nov./Dec. 2002, pp. 2788-2792.
European Search Report for 05425406 dated Sep. 7, 2005.

Affiliated with

Also associated with

Rating

Process for manufacturing a high-quality SOI wafer does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Process for manufacturing a high-quality SOI wafer, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Process for manufacturing a high-quality SOI wafer will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-4153331