Process for manufacturing a DRAM capacitor having an annularly-g

Details Process for manufacturing a DRAM capacitor having an annularly-g Process for manufacturing a DRAM capacitor having an annularly-g

1995-09-26

1998-06-09

Chaudhari, Chandra

Fishing, trapping, and vermin destroying

437919, 437977, H01L 218242

Patent

active

057632863

ABSTRACT:
This invention is a process for fabricating a DRAM capacitor having an annularly-grooved, cup-shaped storage-node plate and a cell plate which covers both inner and outer surfaces of the storage-node plate. A plurality of oxide layers having alternately-varying composition are deposited on top of an in-process DRAM array to form a single sacrificial mold layer. In a preferred embodiment of the invention, ozone TEOS oxide is one of the alternately-varying layers, and plasma-enhanced TEOS oxide is the other. Ozone TEOS oxide etches more rapidly than does plasma-enhanced TEOS oxide, and both types of TEOS oxide are etchable with respect to polycrystalline silicon. Following the deposition of the sacrificial mold layer, the mold layer is patterned and anisotropically etched to form a mold opening in the mold layer. Contact to the storage node of the cell access transistor is made at the bottom of the mold opening. The mold layer is then subjected to a wet etch which etches the alternating oxide layers within the mold layer at different rates. Because of the different etch rates, a plurality of grooves are formed on the surface of the mold opening. A polysilicon layer is then deposited which covers the upper surface of the mold layer and conformally lines the mold opening. Following the removal of the polysilicon layer from the upper surface of the mold layer, the mold layer is etched away so as to expose the outer surface of the polysilicon layer remnant that is to be the storage-node capacitor plate. The capacitor is then completed in a conventional manner.

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Woo, et al., "Selective Etching Technology in in-situ P Doped Poly-Si (SEDOP) for High Density DRAM Capacitors", 1994 Symposium on VLSI Technology Digest of Technical Papers, pp. 25-26.

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