Process for manufacturing a buried gate field effect transistor

Details Process for manufacturing a buried gate field effect transistor Process for manufacturing a buried gate field effect transistor

1983-02-15

1985-03-12

Ozaki, G.

Metal working

Method of mechanical manufacture

Assembling or joining

29574, 29576B, 29576E, 29578, 29591, 148175, 148187, H01L 21265

Patent

active

045036004

ABSTRACT:
A process for manufacturing a buried gate field effect transistor having a small effective gate length, which process enables precise control of the threshold voltage. First, a compound semiconductor crystal having a first impurity region as a source region, a second impurity region as a drain region and a channel layer buried inside the compound semiconductor crystal is prepared by a conventional process. A V-shaped groove is then formed with an etching solution having high selectivity toward the crystal face in the gate region of this compound semiconductor crystal. Onto the inner wall surface of the V-shaped groove, a metal likely to form an alloy type of Schottky junction with the compound semiconductor is vapor-deposited. The resultant structure is heated, while measuring the threshold voltage, to form an alloy type of Schottky junction and for use of this junction as a gate electrode.

REFERENCES:
patent: 3946415 (1976-03-01), Cook
patent: 4265934 (1981-05-01), Ladd
patent: 4301188 (1981-11-01), Niehaus
patent: 4374455 (1983-02-01), Goodman
patent: 4379005 (1983-04-01), Hovel et al.
patent: 4404732 (1983-09-01), Andrade
Inst. Phys. Conf. Ser. No. 63: Chapter 11, Japan, Sep. 20, 1981, Toyoda et al., "An Application of Pt-GaAs Reaction to GaAs ICS", pp. 521-526.
Surface Science 113, Jan. 1982, Takashi Mimura, "The Present Status of Modulation-Doped and Insulated-Gate Field-Effect Transistors in III-V Semiconductors", pp. 454-463, North-Holland Publishing Co.
Electronics Letters, vol. 18, No. 3, Feb. 4, 1982, Tung et al., "High-Speed Two-Dimensional Electron-Gas FET Logic", pp. 109-110.

Affiliated with

Also associated with

Rating

Process for manufacturing a buried gate field effect transistor does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Process for manufacturing a buried gate field effect transistor, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Process for manufacturing a buried gate field effect transistor will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-701279