Metal working – Method of mechanical manufacture – Electrical device making
Reexamination Certificate
2000-11-06
2003-11-25
Shoap, Allan N. (Department: 3724)
Metal working
Method of mechanical manufacture
Electrical device making
C029S830000, C029S831000, C029S842000, C029S847000, C427S096400
Reexamination Certificate
active
06651324
ABSTRACT:
FIELD OF THE INVENTION
This invention relates generally to methods of producing printed circuit boards. More particularly the present invention is a method of producing printed circuit boards having thick copper power circuitry and thin copper signal circuitry on the same board.
BACKGROUND OF THE INVENTION
In the past, high power applications, such as, motor controllers, inverters, converters, power supplies, or other control devices, required a number of circuit boards. Typically, this meant separate boards for power modules which house high-power electrical devices, such as, resistors and semiconductors; and circuit boards for logic or customer interface circuit boards (e.g., motherboard) that house microprocessors or other logic devices for performing control functions. See for example U.S. Pat. No. 5,930,112 to Babinski, et al. that discloses electronic motor controllers in such configuration.
Babinski discloses that the use of multiple circuit boards requires circuit board interconnection systems (e.g., connectors, header assemblies, or other hardware) to interface each circuit board. Such interconnection systems are expensive, bulky, add to the cost of assembly, and can create significant impedance-matching problems in high power applications. For example, motor controllers and high power circuits often require “snubbing” circuits to tune the circuit boards and to reduce the parasitic inductive effects and capacitive effects associated with the circuit board interconnection systems. Hence it is desirable to eliminate the interconnection systems altogether.
Similarly, manufacturers of electronic devices have often required both power circuitry and component circuitry. Component circuitry often requires fine line conductor circuitry. For example, it is common for fine line conductors to be in the order of 0.005 inches wide (127 &mgr;um) and generally with the same width spaces between two conductors. The trend in the industry today is to make the fine line conductors and the spaces between them even narrower as, for example, 0.00025 inches wide (6 um).
Examples of semiconductor chips requiring fine line conductors include flip chips, quad flat package (QFP) chips and ultra ball grid array (uBGA). These semiconductor chip types are desirable because of their high I/O density capability, small profiles, and good electrical performance. However, if the surface of the copper is imperfect, either open or short circuits can be created, resulting in printed circuit boards, which for the most part, are rejected.
Multilayer printed circuit boards (MLB's) have been the subject of much invention in order to provide both high current carrying conductor portions and fine line conductors in a single printed circuit board, although on separate layers. U.S. Pat. No. 5,926,377 to Nakao, et al. discloses MLB's containing separate layers for component signals and power source.
MLB's are typically constructed by interleaving imaged conductive layers such as one containing copper with non-conductive layers such as a partially cured B-stage resin, i.e., a prepreg, into a multilayer sandwich which is then bonded together by applying heat and pressure. The conductive layer, e.g., copper circuitry, does not bond well to the non-conductive B-stage resin prepreg. Often intermediate layers are used to bond the B-stage prepreg to the copper circuitry.
In the formation of multilayer circuit boards, it is often necessary to drill holes through the boards. Defects can occur during such operations due to delamination of layers in the areas immediately surrounding a hole. Additionally, hole cleaning chemicals (typically acidic or reductive) can remove the bonding metal oxide-metal hydroxide layer. This removal leads to partial delamination, known as “pink ring.” When the multilayer structures are exposed to elevated temperatures for extended periods of time, decay of the bond strength may also occur.
U.S. Pat. No. 5,073,456, issued to Palladino, relates to multilayer printed circuit board. The multilayer printed circuit boards, having a number of through-holes, are prepared by forming an electrically conductive copper circuitry on the surface of a dielectric material and forming a layer of oxide, hydroxide or combinations thereof of tin on the copper circuitry, applying a silane bonding mixture to the surface of the metal oxide, metal hydroxide or combination thereof layer or to an insulating layer to be bonded to the copper circuitry, wherein the insulating layer comprises a partially cured thermosetting polymer composition. A number of through holes are formed in the bonded article and the walls of the through holes are metalized to form electrically conductive paths.
U.S. Pat. No. 5,928,790 issued to Bokisa, relates to multilayer printed circuit board. It attempts to improve the adhesion of copper circuitry to a dielectric layer by covering the copper circuitry with a layer of an oxide, hydroxide, of a metal selected from the group consisting of tin, bismuth, lead, indium, gallium, germanium. Bokisa discloses that this method helps in reducing partial delaminations (pink ring) and improves bonding strength for elevated temperatures.
As an alternate to multilayer boards, inventors have used separately attached insulated conductors (e.g. wiring) for power circuits. U.S. Pat. No. 3,646,572 to Burr discloses such an invention. U.S. Pat. No. 6,042,685 to Shinada, et al. extends this concept to multilayer boards by embedding the wiring into an inner layer of the board.
All of these methods are inferior to a method of combining thick power conductor areas with fine resolution conductor areas on a single layer printed circuit board. Thick conductor areas are suited for power or current carrying conductors. The current carrying capacity of a conductor is determined by the cross sectional area of the conductor. A thicker conductor requires less surface of the final printed circuit board so is especially desirable for dense circuitry. Typically a conductor thickness of 0.0003 to 0.0007 inch (9~18 um) is acceptable for fine resolution signal conductors. However, power conductor areas are preferably 0.004 to 0.016 inch (100-400 um) or thicker. These thick conductor areas have been problematic for manufacture of the printed circuit boards. In its elementary form, a printed circuit board includes, as a component, a dielectric layer of an epoxy resin-impregnated woven glass fiber that is known as “prepreg”. On the opposite sides of the prepreg are bonded conductive foil sheets. Subsequently the foil, through a number of photographic processes, is etched to produce conductive paths on the surface of the prepreg layer. When so assembled, the lamination is often called a core or a board.
When preparing a board with thick conductor areas, either the copper foil starts with the required thickness or its thickness must be increased for the thick conductor areas. When starting with a thick profile conductor foil, etching times are long so production is slow and expensive. In addition, the track profile is poor which reduces the ability to create fine resolution conductor areas on the same board. The high conductor profile often interferes with subsequent manufacturing steps. For example high conductor profiles often cause problems with solder mask application, particularly on the corners.
The alternate of using thinner conductor foil, then augmenting the thickness for the thick conductor areas presents similar problems. Such a technique would start with a conductor foil of approximately 0.0028 inch (70 um), imaging and etching the pattern, and then utilize electro-deposition to increase the conductor thickness. This technique requires multiple process steps and produces a product inferior to the invention disclosed herein. For example, the finished conductor thickness formed in this fashion will have inconsistent thickness and poor track profile. Poor track profile reduces the ability to create fine resolution conductor areas. Finally the uneven conductor profile causes problems in subsequent manufacturing ste
Pedretti Giuseppe
Varley Ken
Dunlap Codding & Rogers
Hamilton Isaac
Shoap Allan N.
Viasystems Group, Inc.
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