Active solid-state devices (e.g. – transistors – solid-state diode – Regenerative type switching device – With extended latchup current level
Reexamination Certificate
1998-11-17
2001-03-27
Picardat, Kevin M. (Department: 2823)
Active solid-state devices (e.g., transistors, solid-state diode
Regenerative type switching device
With extended latchup current level
C257S213000, C257S288000, C257S341000
Reexamination Certificate
active
06207974
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to semiconductor devices and, more specifically, to MOS gate controlled reference (MOS-gated) semiconductor devices formed using a reduced number of masking steps with only a minimal number of critical alignments.
MOS-gated devices are well-known in the art and include devices such as the MOS-gated devices described in U.S. Pat. No. 5,795,793, issued Aug. 18, 1998. These devices include power MOSFETs, MOS-gated thyristors, insulated gate bipolar transistors (IGBTs), gate turn-off devices and the like.
The manufacturing processes for such devices typically include a number of lithographic masking steps which include critical mask alignment steps. Each of these critical alignment steps add manufacturing time and expense as well as provide possible sources of device defects.
It is therefore desirable to minimize the number of critical alignments necessary as well as reduce the number of masking steps to improve the manufacturing yield and reduce the manufacturing cost.
SUMMARY OF THE INVENTION
The present invention provides a novel process for the manufacture of P-channel MOS-gated power devices by forming P-channel device cells using only three or four mask steps with only one critical alignment at the contact mask step.
A gate oxide layer and a polysilicon layer are formed atop a P− silicon substrate. A first photolithographic masking step defines an N-type body or channel region of each of the cells or strips of the device as well as a P+ source region disposed within the N-type body region of the MOSFET cell.
A second photolithographic masking step is then employed which is aligned to a small central area above the P+ regions of each of the cells or strips of the device. An anisotropic oxide etch forms openings in a protective oxide layer covering the device which reach the surface of the silicon. An anisotropic silicon etch follows which causes a shallow hole in the surface of the silicon centered on the P+ regions. The hole is deep enough to cut through the P+ regions and reach the underlying N-type channels or body regions. The alignment of the second mask, which is the contact mask, is the only critical alignment in the process.
A heavy base contact implant is carried out through the contact window after the hole has been etched in the silicon but before metal is deposited on the wafer. This heavy base contact implant is then followed by an isotropic etch which undercuts the protective oxide above the gate oxide to expose shoulders at the silicon surface of the chip which surround the etched openings into the N+cell regions.
Thereafter, a conductive layer, which may be metal, is deposited over the surface and fills the holes through the P+ region, thereby contacting the underlying N body regions and overlaps the shoulders surrounding the P+ source regions at the silicon surface. Consequently, a good contact is made to the P+ source and to the underlying N region. Note that this contact between the N underlying body region and the P+ source region is desirable in order to short circuit the parasitic transistor which inherently appears in each cell structure of a MOS gated device.
A third mask is used to pattern the metal, followed by a sinter and backside metallization. No anneal is required prior to metallization because the sinter temperature is sufficiently high to activate enough dopant to achieve low contact resistance between the metal and body regions but is low enough to be tolerated after the metal is deposited.
Other features and advantages of the present invention will become apparent from the following description of the invention which refers to the accompanying drawings.
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A High Density Self-Aligned 4-Mask Planar VDMOS Process, D. Kinzer, J.S. Ajit, K. Wager, D. Asselanis, Proceedings of the 8th International Symposium on Power Semiconductor Devices and IC'S (ISPSD) Maui, Hawaii, May 20-23, 1996, pp. 243-246 XP000598433, Salama C A T; Williams R K (Eds) p. 244, Colonne De Gauche; Figure 1.
Collins D. M.
International Rectifier Corp.
Ostrolenk Faber Gerb & Soffen, LLP
Picardat Kevin M.
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