Process for managing a hierarcy of memories

Details Process for managing a hierarcy of memories Process for managing a hierarcy of memories

1994-07-15

1996-10-22

Robertson, David L.

395471, 395472, 395473, 395447, 395448, 395449, G06I 1300

Patent

active

055686338

ABSTRACT:
The process for exchanges between the levels in a hierarchy of memories comprising at least one intermediate level in the hierarchy linked to a higher level in the hierarchy and to a lower level in the hierarchy, with each level in the hierarchy being divided into memories (3, 5, 6) which are in turn divided into blocks (10) containing information (11) associated with addresses (Ad), with the blocks of the memories on the higher level and on the intermediate level in the hierarchy containing copies of the information held in the blocks at the corresponding addresses on the lower level in the hierarchy, and during a modification of a piece of information in a block (10.32) of a memory on the higher level in the hierarchy, invalidating at least some of the information at the corresponding addresses of other memories on the higher level in the hierarchy, and managing an update or an invalidation of the information at the corresponding addresses on the intermediate level and the lower level in the hierarchy, depending on the usefulness of the update.

REFERENCES:
patent: 4445174 (1984-04-01), Fletcher
patent: 5226144 (1993-07-01), Moriwaki et al.
patent: 5228136 (1993-07-01), Shimizu et al.
patent: 5241664 (1993-08-01), Ohba et al.
patent: 5291442 (1994-03-01), Emma et al.
Eggers et al., "Evaluating the Performance of Four Snooping Cache Coherency Protocols", from Proceedings, 17 Jun. 1989, No. 3, Washington, US.

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